1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2011 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <hwconfig.h> 9 #include <asm/mmu.h> 10 #include <fsl_ddr_sdram.h> 11 #include <fsl_ddr_dimm_params.h> 12 #include <asm/fsl_law.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 struct board_specific_parameters { 17 u32 n_ranks; 18 u32 datarate_mhz_high; 19 u32 clk_adjust; 20 u32 wrlvl_start; 21 u32 cpo; 22 u32 write_data_delay; 23 u32 force_2t; 24 }; 25 26 /* 27 * This table contains all valid speeds we want to override with board 28 * specific parameters. datarate_mhz_high values need to be in ascending order 29 * for each n_ranks group. 30 * 31 * ranges for parameters: 32 * wr_data_delay = 0-6 33 * clk adjust = 0-8 34 * cpo 2-0x1E (30) 35 */ 36 static const struct board_specific_parameters dimm0[] = { 37 /* 38 * memory controller 0 39 * num| hi| clk| wrlvl | cpo |wrdata|2T 40 * ranks| mhz|adjst| start | delay| 41 */ 42 {2, 750, 3, 5, 0xff, 2, 0}, 43 {2, 1250, 4, 6, 0xff, 2, 0}, 44 {2, 1350, 5, 7, 0xff, 2, 0}, 45 {2, 1666, 5, 8, 0xff, 2, 0}, 46 {} 47 }; 48 49 void fsl_ddr_board_options(memctl_options_t *popts, 50 dimm_params_t *pdimm, 51 unsigned int ctrl_num) 52 { 53 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 54 ulong ddr_freq; 55 56 if (ctrl_num) { 57 printf("Wrong parameter for controller number %d", ctrl_num); 58 return; 59 } 60 if (!pdimm->n_ranks) 61 return; 62 63 pbsp = dimm0; 64 65 /* 66 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 67 * freqency and n_banks specified in board_specific_parameters table. 68 */ 69 ddr_freq = get_ddr_freq(0) / 1000000; 70 while (pbsp->datarate_mhz_high) { 71 if (pbsp->n_ranks == pdimm->n_ranks) { 72 if (ddr_freq <= pbsp->datarate_mhz_high) { 73 popts->cpo_override = pbsp->cpo; 74 popts->write_data_delay = 75 pbsp->write_data_delay; 76 popts->clk_adjust = pbsp->clk_adjust; 77 popts->wrlvl_start = pbsp->wrlvl_start; 78 popts->twot_en = pbsp->force_2t; 79 goto found; 80 } 81 pbsp_highest = pbsp; 82 } 83 pbsp++; 84 } 85 86 if (pbsp_highest) { 87 printf("Error: board specific timing not found " 88 "for data rate %lu MT/s!\n" 89 "Trying to use the highest speed (%u) parameters\n", 90 ddr_freq, pbsp_highest->datarate_mhz_high); 91 popts->cpo_override = pbsp_highest->cpo; 92 popts->write_data_delay = pbsp_highest->write_data_delay; 93 popts->clk_adjust = pbsp_highest->clk_adjust; 94 popts->wrlvl_start = pbsp_highest->wrlvl_start; 95 popts->twot_en = pbsp_highest->force_2t; 96 } else { 97 panic("DIMM is not supported by this board"); 98 } 99 100 found: 101 /* 102 * Factors to consider for half-strength driver enable: 103 * - number of DIMMs installed 104 */ 105 popts->half_strength_driver_enable = 0; 106 /* Write leveling override */ 107 popts->wrlvl_override = 1; 108 popts->wrlvl_sample = 0xf; 109 110 /* Rtt and Rtt_WR override */ 111 popts->rtt_override = 0; 112 113 /* Enable ZQ calibration */ 114 popts->zq_en = 1; 115 116 /* DHC_EN =1, ODT = 60 Ohm */ 117 popts->ddr_cdr1 = DDR_CDR1_DHC_EN; 118 } 119 120 int dram_init(void) 121 { 122 phys_size_t dram_size = 0; 123 124 puts("Initializing...."); 125 126 if (fsl_use_spd()) { 127 puts("using SPD\n"); 128 dram_size = fsl_ddr_sdram(); 129 } else { 130 puts("no SPD and fixed parameters\n"); 131 return -ENXIO; 132 } 133 134 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 135 dram_size *= 0x100000; 136 137 debug(" DDR: "); 138 gd->ram_size = dram_size; 139 140 return 0; 141 } 142