1 /** 2 * Copyright 2011 Freescale Semiconductor 3 * Author: Mingkai Hu <Mingkai.hu@freescale.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the Free 7 * Software Foundation; either version 2 of the License, or (at your option) 8 * any later version. 9 * 10 * This file provides support for the board-specific CPLD used on some Freescale 11 * reference boards. 12 * 13 * The following macros need to be defined: 14 * 15 * CPLD_BASE - The virtual address of the base of the CPLD register map 16 * 17 */ 18 19 #include <common.h> 20 #include <command.h> 21 #include <asm/io.h> 22 23 #include "cpld.h" 24 25 static u8 __cpld_read(unsigned int reg) 26 { 27 void *p = (void *)CPLD_BASE; 28 29 return in_8(p + reg); 30 } 31 u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); 32 33 static void __cpld_write(unsigned int reg, u8 value) 34 { 35 void *p = (void *)CPLD_BASE; 36 37 out_8(p + reg, value); 38 } 39 void cpld_write(unsigned int reg, u8 value) 40 __attribute__((weak, alias("__cpld_write"))); 41 42 /* 43 * Reset the board. This honors the por_cfg registers. 44 */ 45 void __cpld_reset(void) 46 { 47 CPLD_WRITE(system_rst, 1); 48 } 49 void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); 50 51 /** 52 * Set the boot bank to the alternate bank 53 */ 54 void __cpld_set_altbank(void) 55 { 56 CPLD_WRITE(fbank_sel, 1); 57 } 58 void cpld_set_altbank(void) 59 __attribute__((weak, alias("__cpld_set_altbank"))); 60 61 /** 62 * Set the boot bank to the default bank 63 */ 64 void __cpld_clear_altbank(void) 65 { 66 CPLD_WRITE(fbank_sel, 0); 67 } 68 void cpld_clear_altbank(void) 69 __attribute__((weak, alias("__cpld_clear_altbank"))); 70 71 #ifdef DEBUG 72 static void cpld_dump_regs(void) 73 { 74 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); 75 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); 76 printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); 77 printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); 78 printf("wd_cfg = 0x%02x\n", CPLD_READ(wd_cfg)); 79 printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); 80 printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); 81 printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); 82 printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); 83 printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); 84 printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk)); 85 printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); 86 printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); 87 printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2))); 88 putc('\n'); 89 } 90 #endif 91 92 int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 93 { 94 int rc = 0; 95 unsigned int i; 96 97 if (argc <= 1) 98 return cmd_usage(cmdtp); 99 100 if (strcmp(argv[1], "reset") == 0) { 101 if (strcmp(argv[2], "altbank") == 0) 102 cpld_set_altbank(); 103 else 104 cpld_clear_altbank(); 105 106 cpld_reset(); 107 } else if (strcmp(argv[1], "watchdog") == 0) { 108 static char *period[8] = {"1ms", "10ms", "30ms", "disable", 109 "100ms", "1s", "10s", "60s"}; 110 for (i = 0; i < ARRAY_SIZE(period); i++) { 111 if (strcmp(argv[2], period[i]) == 0) 112 CPLD_WRITE(wd_cfg, i); 113 } 114 } else if (strcmp(argv[1], "lane_mux") == 0) { 115 u32 lane = simple_strtoul(argv[2], NULL, 16); 116 u8 val = (u8)simple_strtoul(argv[3], NULL, 16); 117 u8 reg = CPLD_READ(serdes_mux); 118 119 switch (lane) { 120 case 0x6: 121 reg &= ~SERDES_MUX_LANE_6_MASK; 122 reg |= val << SERDES_MUX_LANE_6_SHIFT; 123 break; 124 case 0xa: 125 reg &= ~SERDES_MUX_LANE_A_MASK; 126 reg |= val << SERDES_MUX_LANE_A_SHIFT; 127 break; 128 case 0xc: 129 reg &= ~SERDES_MUX_LANE_C_MASK; 130 reg |= val << SERDES_MUX_LANE_C_SHIFT; 131 break; 132 case 0xd: 133 reg &= ~SERDES_MUX_LANE_D_MASK; 134 reg |= val << SERDES_MUX_LANE_D_SHIFT; 135 break; 136 default: 137 printf("Invalid value\n"); 138 break; 139 } 140 141 CPLD_WRITE(serdes_mux, reg); 142 #ifdef DEBUG 143 } else if (strcmp(argv[1], "dump") == 0) { 144 cpld_dump_regs(); 145 #endif 146 } else 147 rc = cmd_usage(cmdtp); 148 149 return rc; 150 } 151 152 U_BOOT_CMD( 153 cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, 154 "Reset the board or pin mulexing selection using the CPLD sequencer", 155 "reset - hard reset to default bank\n" 156 "cpld_cmd reset altbank - reset to alternate bank\n" 157 "cpld_cmd watchdog <watchdog_period> - set the watchdog period\n" 158 " period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n" 159 "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n" 160 " lane 6: 0 -> slot1 (Default)\n" 161 " 1 -> SGMII\n" 162 " lane a: 0 -> slot2 (Default)\n" 163 " 1 -> AURORA\n" 164 " lane c: 0 -> slot2 (Default)\n" 165 " 1 -> SATA0\n" 166 " lane d: 0 -> slot2 (Default)\n" 167 " 1 -> SATA1\n" 168 #ifdef DEBUG 169 "cpld_cmd dump - display the CPLD registers\n" 170 #endif 171 ); 172