1 /** 2 * Copyright 2011 Freescale Semiconductor 3 * Author: Mingkai Hu <Mingkai.hu@freescale.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the Free 7 * Software Foundation; either version 2 of the License, or (at your option) 8 * any later version. 9 * 10 * This file provides support for the board-specific CPLD used on some Freescale 11 * reference boards. 12 * 13 * The following macros need to be defined: 14 * 15 * CPLD_BASE - The virtual address of the base of the CPLD register map 16 * 17 */ 18 19 #include <common.h> 20 #include <command.h> 21 #include <asm/io.h> 22 23 #include "cpld.h" 24 25 static u8 __cpld_read(unsigned int reg) 26 { 27 void *p = (void *)CPLD_BASE; 28 29 return in_8(p + reg); 30 } 31 u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); 32 33 static void __cpld_write(unsigned int reg, u8 value) 34 { 35 void *p = (void *)CPLD_BASE; 36 37 out_8(p + reg, value); 38 } 39 void cpld_write(unsigned int reg, u8 value) 40 __attribute__((weak, alias("__cpld_write"))); 41 42 /* 43 * Reset the board. This honors the por_cfg registers. 44 */ 45 void __cpld_reset(void) 46 { 47 CPLD_WRITE(system_rst, 1); 48 } 49 void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); 50 51 /** 52 * Set the boot bank to the alternate bank 53 */ 54 void __cpld_set_altbank(void) 55 { 56 u8 reg5 = CPLD_READ(sw_ctl_on); 57 58 CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); 59 CPLD_WRITE(fbank_sel, 1); 60 CPLD_WRITE(system_rst, 1); 61 } 62 void cpld_set_altbank(void) 63 __attribute__((weak, alias("__cpld_set_altbank"))); 64 65 /** 66 * Set the boot bank to the default bank 67 */ 68 void __cpld_set_defbank(void) 69 { 70 CPLD_WRITE(system_rst_default, 1); 71 } 72 void cpld_set_defbank(void) 73 __attribute__((weak, alias("__cpld_set_defbank"))); 74 75 #ifdef DEBUG 76 static void cpld_dump_regs(void) 77 { 78 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); 79 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); 80 printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); 81 printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); 82 printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); 83 printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); 84 printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); 85 printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); 86 printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); 87 printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk)); 88 printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); 89 printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); 90 printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2))); 91 putc('\n'); 92 } 93 #endif 94 95 int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 96 { 97 int rc = 0; 98 99 if (argc <= 1) 100 return cmd_usage(cmdtp); 101 102 if (strcmp(argv[1], "reset") == 0) { 103 if (strcmp(argv[2], "altbank") == 0) 104 cpld_set_altbank(); 105 else 106 cpld_set_defbank(); 107 } else if (strcmp(argv[1], "lane_mux") == 0) { 108 u32 lane = simple_strtoul(argv[2], NULL, 16); 109 u8 val = (u8)simple_strtoul(argv[3], NULL, 16); 110 u8 reg = CPLD_READ(serdes_mux); 111 112 switch (lane) { 113 case 0x6: 114 reg &= ~SERDES_MUX_LANE_6_MASK; 115 reg |= val << SERDES_MUX_LANE_6_SHIFT; 116 break; 117 case 0xa: 118 reg &= ~SERDES_MUX_LANE_A_MASK; 119 reg |= val << SERDES_MUX_LANE_A_SHIFT; 120 break; 121 case 0xc: 122 reg &= ~SERDES_MUX_LANE_C_MASK; 123 reg |= val << SERDES_MUX_LANE_C_SHIFT; 124 break; 125 case 0xd: 126 reg &= ~SERDES_MUX_LANE_D_MASK; 127 reg |= val << SERDES_MUX_LANE_D_SHIFT; 128 break; 129 default: 130 printf("Invalid value\n"); 131 break; 132 } 133 134 CPLD_WRITE(serdes_mux, reg); 135 #ifdef DEBUG 136 } else if (strcmp(argv[1], "dump") == 0) { 137 cpld_dump_regs(); 138 #endif 139 } else 140 rc = cmd_usage(cmdtp); 141 142 return rc; 143 } 144 145 U_BOOT_CMD( 146 cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, 147 "Reset the board or pin mulexing selection using the CPLD sequencer", 148 "reset - hard reset to default bank\n" 149 "cpld_cmd reset altbank - reset to alternate bank\n" 150 "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n" 151 " lane 6: 0 -> slot1\n" 152 " 1 -> SGMII (Default)\n" 153 " lane a: 0 -> slot2\n" 154 " 1 -> AURORA (Default)\n" 155 " lane c: 0 -> slot2\n" 156 " 1 -> SATA0 (Default)\n" 157 " lane d: 0 -> slot2\n" 158 " 1 -> SATA1 (Default)\n" 159 #ifdef DEBUG 160 "cpld_cmd dump - display the CPLD registers\n" 161 #endif 162 ); 163