1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 24f1d1b7dSMingkai Hu /** 34f1d1b7dSMingkai Hu * Copyright 2011 Freescale Semiconductor 44f1d1b7dSMingkai Hu * Author: Mingkai Hu <Mingkai.hu@freescale.com> 54f1d1b7dSMingkai Hu * 64f1d1b7dSMingkai Hu * This file provides support for the board-specific CPLD used on some Freescale 74f1d1b7dSMingkai Hu * reference boards. 84f1d1b7dSMingkai Hu * 94f1d1b7dSMingkai Hu * The following macros need to be defined: 104f1d1b7dSMingkai Hu * 114f1d1b7dSMingkai Hu * CPLD_BASE - The virtual address of the base of the CPLD register map 124f1d1b7dSMingkai Hu */ 134f1d1b7dSMingkai Hu 144f1d1b7dSMingkai Hu #include <common.h> 154f1d1b7dSMingkai Hu #include <command.h> 164f1d1b7dSMingkai Hu #include <asm/io.h> 174f1d1b7dSMingkai Hu 184f1d1b7dSMingkai Hu #include "cpld.h" 194f1d1b7dSMingkai Hu 204f1d1b7dSMingkai Hu static u8 __cpld_read(unsigned int reg) 214f1d1b7dSMingkai Hu { 224f1d1b7dSMingkai Hu void *p = (void *)CPLD_BASE; 234f1d1b7dSMingkai Hu 244f1d1b7dSMingkai Hu return in_8(p + reg); 254f1d1b7dSMingkai Hu } 264f1d1b7dSMingkai Hu u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); 274f1d1b7dSMingkai Hu 284f1d1b7dSMingkai Hu static void __cpld_write(unsigned int reg, u8 value) 294f1d1b7dSMingkai Hu { 304f1d1b7dSMingkai Hu void *p = (void *)CPLD_BASE; 314f1d1b7dSMingkai Hu 324f1d1b7dSMingkai Hu out_8(p + reg, value); 334f1d1b7dSMingkai Hu } 344f1d1b7dSMingkai Hu void cpld_write(unsigned int reg, u8 value) 354f1d1b7dSMingkai Hu __attribute__((weak, alias("__cpld_write"))); 364f1d1b7dSMingkai Hu 374f1d1b7dSMingkai Hu /* 384f1d1b7dSMingkai Hu * Reset the board. This honors the por_cfg registers. 394f1d1b7dSMingkai Hu */ 404f1d1b7dSMingkai Hu void __cpld_reset(void) 414f1d1b7dSMingkai Hu { 424f1d1b7dSMingkai Hu CPLD_WRITE(system_rst, 1); 434f1d1b7dSMingkai Hu } 444f1d1b7dSMingkai Hu void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); 454f1d1b7dSMingkai Hu 464f1d1b7dSMingkai Hu /** 474f1d1b7dSMingkai Hu * Set the boot bank to the alternate bank 484f1d1b7dSMingkai Hu */ 494f1d1b7dSMingkai Hu void __cpld_set_altbank(void) 504f1d1b7dSMingkai Hu { 51ba50fee6SShaohui Xie u8 reg5 = CPLD_READ(sw_ctl_on); 52ba50fee6SShaohui Xie 53ba50fee6SShaohui Xie CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); 544f1d1b7dSMingkai Hu CPLD_WRITE(fbank_sel, 1); 55ba50fee6SShaohui Xie CPLD_WRITE(system_rst, 1); 564f1d1b7dSMingkai Hu } 574f1d1b7dSMingkai Hu void cpld_set_altbank(void) 584f1d1b7dSMingkai Hu __attribute__((weak, alias("__cpld_set_altbank"))); 594f1d1b7dSMingkai Hu 604f1d1b7dSMingkai Hu /** 614f1d1b7dSMingkai Hu * Set the boot bank to the default bank 624f1d1b7dSMingkai Hu */ 63ba50fee6SShaohui Xie void __cpld_set_defbank(void) 644f1d1b7dSMingkai Hu { 65ba50fee6SShaohui Xie CPLD_WRITE(system_rst_default, 1); 664f1d1b7dSMingkai Hu } 67ba50fee6SShaohui Xie void cpld_set_defbank(void) 68ba50fee6SShaohui Xie __attribute__((weak, alias("__cpld_set_defbank"))); 694f1d1b7dSMingkai Hu 704f1d1b7dSMingkai Hu #ifdef DEBUG 714f1d1b7dSMingkai Hu static void cpld_dump_regs(void) 724f1d1b7dSMingkai Hu { 734f1d1b7dSMingkai Hu printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); 744f1d1b7dSMingkai Hu printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); 754f1d1b7dSMingkai Hu printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); 764f1d1b7dSMingkai Hu printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); 774f1d1b7dSMingkai Hu printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); 784f1d1b7dSMingkai Hu printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); 794f1d1b7dSMingkai Hu printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); 804f1d1b7dSMingkai Hu printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); 814f1d1b7dSMingkai Hu printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); 824f1d1b7dSMingkai Hu printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk)); 834f1d1b7dSMingkai Hu printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); 844f1d1b7dSMingkai Hu printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); 854f1d1b7dSMingkai Hu printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2))); 864f1d1b7dSMingkai Hu putc('\n'); 874f1d1b7dSMingkai Hu } 884f1d1b7dSMingkai Hu #endif 894f1d1b7dSMingkai Hu 904f1d1b7dSMingkai Hu int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 914f1d1b7dSMingkai Hu { 924f1d1b7dSMingkai Hu int rc = 0; 934f1d1b7dSMingkai Hu 944f1d1b7dSMingkai Hu if (argc <= 1) 954f1d1b7dSMingkai Hu return cmd_usage(cmdtp); 964f1d1b7dSMingkai Hu 974f1d1b7dSMingkai Hu if (strcmp(argv[1], "reset") == 0) { 984f1d1b7dSMingkai Hu if (strcmp(argv[2], "altbank") == 0) 994f1d1b7dSMingkai Hu cpld_set_altbank(); 1004f1d1b7dSMingkai Hu else 101ba50fee6SShaohui Xie cpld_set_defbank(); 1024f1d1b7dSMingkai Hu } else if (strcmp(argv[1], "lane_mux") == 0) { 1034f1d1b7dSMingkai Hu u32 lane = simple_strtoul(argv[2], NULL, 16); 1044f1d1b7dSMingkai Hu u8 val = (u8)simple_strtoul(argv[3], NULL, 16); 1054f1d1b7dSMingkai Hu u8 reg = CPLD_READ(serdes_mux); 1064f1d1b7dSMingkai Hu 1074f1d1b7dSMingkai Hu switch (lane) { 1084f1d1b7dSMingkai Hu case 0x6: 1094f1d1b7dSMingkai Hu reg &= ~SERDES_MUX_LANE_6_MASK; 1104f1d1b7dSMingkai Hu reg |= val << SERDES_MUX_LANE_6_SHIFT; 1114f1d1b7dSMingkai Hu break; 1124f1d1b7dSMingkai Hu case 0xa: 1134f1d1b7dSMingkai Hu reg &= ~SERDES_MUX_LANE_A_MASK; 1144f1d1b7dSMingkai Hu reg |= val << SERDES_MUX_LANE_A_SHIFT; 1154f1d1b7dSMingkai Hu break; 1164f1d1b7dSMingkai Hu case 0xc: 1174f1d1b7dSMingkai Hu reg &= ~SERDES_MUX_LANE_C_MASK; 1184f1d1b7dSMingkai Hu reg |= val << SERDES_MUX_LANE_C_SHIFT; 1194f1d1b7dSMingkai Hu break; 1204f1d1b7dSMingkai Hu case 0xd: 1214f1d1b7dSMingkai Hu reg &= ~SERDES_MUX_LANE_D_MASK; 1224f1d1b7dSMingkai Hu reg |= val << SERDES_MUX_LANE_D_SHIFT; 1234f1d1b7dSMingkai Hu break; 1244f1d1b7dSMingkai Hu default: 1254f1d1b7dSMingkai Hu printf("Invalid value\n"); 1264f1d1b7dSMingkai Hu break; 1274f1d1b7dSMingkai Hu } 1284f1d1b7dSMingkai Hu 1294f1d1b7dSMingkai Hu CPLD_WRITE(serdes_mux, reg); 1304f1d1b7dSMingkai Hu #ifdef DEBUG 1314f1d1b7dSMingkai Hu } else if (strcmp(argv[1], "dump") == 0) { 1324f1d1b7dSMingkai Hu cpld_dump_regs(); 1334f1d1b7dSMingkai Hu #endif 1344f1d1b7dSMingkai Hu } else 1354f1d1b7dSMingkai Hu rc = cmd_usage(cmdtp); 1364f1d1b7dSMingkai Hu 1374f1d1b7dSMingkai Hu return rc; 1384f1d1b7dSMingkai Hu } 1394f1d1b7dSMingkai Hu 1404f1d1b7dSMingkai Hu U_BOOT_CMD( 1414f1d1b7dSMingkai Hu cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, 1424f1d1b7dSMingkai Hu "Reset the board or pin mulexing selection using the CPLD sequencer", 1434f1d1b7dSMingkai Hu "reset - hard reset to default bank\n" 1444f1d1b7dSMingkai Hu "cpld_cmd reset altbank - reset to alternate bank\n" 1454f1d1b7dSMingkai Hu "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n" 14660820457SShaohui Xie " lane 6: 0 -> slot1\n" 14760820457SShaohui Xie " 1 -> SGMII (Default)\n" 14860820457SShaohui Xie " lane a: 0 -> slot2\n" 14960820457SShaohui Xie " 1 -> AURORA (Default)\n" 15060820457SShaohui Xie " lane c: 0 -> slot2\n" 15160820457SShaohui Xie " 1 -> SATA0 (Default)\n" 15260820457SShaohui Xie " lane d: 0 -> slot2\n" 15360820457SShaohui Xie " 1 -> SATA1 (Default)\n" 1544f1d1b7dSMingkai Hu #ifdef DEBUG 1554f1d1b7dSMingkai Hu "cpld_cmd dump - display the CPLD registers\n" 1564f1d1b7dSMingkai Hu #endif 1574f1d1b7dSMingkai Hu ); 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