14f1d1b7dSMingkai Hu /** 24f1d1b7dSMingkai Hu * Copyright 2011 Freescale Semiconductor 34f1d1b7dSMingkai Hu * Author: Mingkai Hu <Mingkai.hu@freescale.com> 44f1d1b7dSMingkai Hu * 54f1d1b7dSMingkai Hu * This program is free software; you can redistribute it and/or modify it 64f1d1b7dSMingkai Hu * under the terms of the GNU General Public License as published by the Free 74f1d1b7dSMingkai Hu * Software Foundation; either version 2 of the License, or (at your option) 84f1d1b7dSMingkai Hu * any later version. 94f1d1b7dSMingkai Hu * 104f1d1b7dSMingkai Hu * This file provides support for the board-specific CPLD used on some Freescale 114f1d1b7dSMingkai Hu * reference boards. 124f1d1b7dSMingkai Hu * 134f1d1b7dSMingkai Hu * The following macros need to be defined: 144f1d1b7dSMingkai Hu * 154f1d1b7dSMingkai Hu * CPLD_BASE - The virtual address of the base of the CPLD register map 164f1d1b7dSMingkai Hu * 174f1d1b7dSMingkai Hu */ 184f1d1b7dSMingkai Hu 194f1d1b7dSMingkai Hu #include <common.h> 204f1d1b7dSMingkai Hu #include <command.h> 214f1d1b7dSMingkai Hu #include <asm/io.h> 224f1d1b7dSMingkai Hu 234f1d1b7dSMingkai Hu #include "cpld.h" 244f1d1b7dSMingkai Hu 254f1d1b7dSMingkai Hu static u8 __cpld_read(unsigned int reg) 264f1d1b7dSMingkai Hu { 274f1d1b7dSMingkai Hu void *p = (void *)CPLD_BASE; 284f1d1b7dSMingkai Hu 294f1d1b7dSMingkai Hu return in_8(p + reg); 304f1d1b7dSMingkai Hu } 314f1d1b7dSMingkai Hu u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); 324f1d1b7dSMingkai Hu 334f1d1b7dSMingkai Hu static void __cpld_write(unsigned int reg, u8 value) 344f1d1b7dSMingkai Hu { 354f1d1b7dSMingkai Hu void *p = (void *)CPLD_BASE; 364f1d1b7dSMingkai Hu 374f1d1b7dSMingkai Hu out_8(p + reg, value); 384f1d1b7dSMingkai Hu } 394f1d1b7dSMingkai Hu void cpld_write(unsigned int reg, u8 value) 404f1d1b7dSMingkai Hu __attribute__((weak, alias("__cpld_write"))); 414f1d1b7dSMingkai Hu 424f1d1b7dSMingkai Hu /* 434f1d1b7dSMingkai Hu * Reset the board. This honors the por_cfg registers. 444f1d1b7dSMingkai Hu */ 454f1d1b7dSMingkai Hu void __cpld_reset(void) 464f1d1b7dSMingkai Hu { 474f1d1b7dSMingkai Hu CPLD_WRITE(system_rst, 1); 484f1d1b7dSMingkai Hu } 494f1d1b7dSMingkai Hu void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); 504f1d1b7dSMingkai Hu 514f1d1b7dSMingkai Hu /** 524f1d1b7dSMingkai Hu * Set the boot bank to the alternate bank 534f1d1b7dSMingkai Hu */ 544f1d1b7dSMingkai Hu void __cpld_set_altbank(void) 554f1d1b7dSMingkai Hu { 56ba50fee6SShaohui Xie u8 reg5 = CPLD_READ(sw_ctl_on); 57ba50fee6SShaohui Xie 58ba50fee6SShaohui Xie CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); 594f1d1b7dSMingkai Hu CPLD_WRITE(fbank_sel, 1); 60ba50fee6SShaohui Xie CPLD_WRITE(system_rst, 1); 614f1d1b7dSMingkai Hu } 624f1d1b7dSMingkai Hu void cpld_set_altbank(void) 634f1d1b7dSMingkai Hu __attribute__((weak, alias("__cpld_set_altbank"))); 644f1d1b7dSMingkai Hu 654f1d1b7dSMingkai Hu /** 664f1d1b7dSMingkai Hu * Set the boot bank to the default bank 674f1d1b7dSMingkai Hu */ 68ba50fee6SShaohui Xie void __cpld_set_defbank(void) 694f1d1b7dSMingkai Hu { 70ba50fee6SShaohui Xie CPLD_WRITE(system_rst_default, 1); 714f1d1b7dSMingkai Hu } 72ba50fee6SShaohui Xie void cpld_set_defbank(void) 73ba50fee6SShaohui Xie __attribute__((weak, alias("__cpld_set_defbank"))); 744f1d1b7dSMingkai Hu 754f1d1b7dSMingkai Hu #ifdef DEBUG 764f1d1b7dSMingkai Hu static void cpld_dump_regs(void) 774f1d1b7dSMingkai Hu { 784f1d1b7dSMingkai Hu printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); 794f1d1b7dSMingkai Hu printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); 804f1d1b7dSMingkai Hu printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); 814f1d1b7dSMingkai Hu printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); 824f1d1b7dSMingkai Hu printf("wd_cfg = 0x%02x\n", CPLD_READ(wd_cfg)); 834f1d1b7dSMingkai Hu printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); 844f1d1b7dSMingkai Hu printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); 854f1d1b7dSMingkai Hu printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); 864f1d1b7dSMingkai Hu printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); 874f1d1b7dSMingkai Hu printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); 884f1d1b7dSMingkai Hu printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk)); 894f1d1b7dSMingkai Hu printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); 904f1d1b7dSMingkai Hu printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); 914f1d1b7dSMingkai Hu printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2))); 924f1d1b7dSMingkai Hu putc('\n'); 934f1d1b7dSMingkai Hu } 944f1d1b7dSMingkai Hu #endif 954f1d1b7dSMingkai Hu 964f1d1b7dSMingkai Hu int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 974f1d1b7dSMingkai Hu { 984f1d1b7dSMingkai Hu int rc = 0; 994f1d1b7dSMingkai Hu unsigned int i; 1004f1d1b7dSMingkai Hu 1014f1d1b7dSMingkai Hu if (argc <= 1) 1024f1d1b7dSMingkai Hu return cmd_usage(cmdtp); 1034f1d1b7dSMingkai Hu 1044f1d1b7dSMingkai Hu if (strcmp(argv[1], "reset") == 0) { 1054f1d1b7dSMingkai Hu if (strcmp(argv[2], "altbank") == 0) 1064f1d1b7dSMingkai Hu cpld_set_altbank(); 1074f1d1b7dSMingkai Hu else 108ba50fee6SShaohui Xie cpld_set_defbank(); 1094f1d1b7dSMingkai Hu } else if (strcmp(argv[1], "watchdog") == 0) { 1104f1d1b7dSMingkai Hu static char *period[8] = {"1ms", "10ms", "30ms", "disable", 1114f1d1b7dSMingkai Hu "100ms", "1s", "10s", "60s"}; 1124f1d1b7dSMingkai Hu for (i = 0; i < ARRAY_SIZE(period); i++) { 1134f1d1b7dSMingkai Hu if (strcmp(argv[2], period[i]) == 0) 1144f1d1b7dSMingkai Hu CPLD_WRITE(wd_cfg, i); 1154f1d1b7dSMingkai Hu } 1164f1d1b7dSMingkai Hu } else if (strcmp(argv[1], "lane_mux") == 0) { 1174f1d1b7dSMingkai Hu u32 lane = simple_strtoul(argv[2], NULL, 16); 1184f1d1b7dSMingkai Hu u8 val = (u8)simple_strtoul(argv[3], NULL, 16); 1194f1d1b7dSMingkai Hu u8 reg = CPLD_READ(serdes_mux); 1204f1d1b7dSMingkai Hu 1214f1d1b7dSMingkai Hu switch (lane) { 1224f1d1b7dSMingkai Hu case 0x6: 1234f1d1b7dSMingkai Hu reg &= ~SERDES_MUX_LANE_6_MASK; 1244f1d1b7dSMingkai Hu reg |= val << SERDES_MUX_LANE_6_SHIFT; 1254f1d1b7dSMingkai Hu break; 1264f1d1b7dSMingkai Hu case 0xa: 1274f1d1b7dSMingkai Hu reg &= ~SERDES_MUX_LANE_A_MASK; 1284f1d1b7dSMingkai Hu reg |= val << SERDES_MUX_LANE_A_SHIFT; 1294f1d1b7dSMingkai Hu break; 1304f1d1b7dSMingkai Hu case 0xc: 1314f1d1b7dSMingkai Hu reg &= ~SERDES_MUX_LANE_C_MASK; 1324f1d1b7dSMingkai Hu reg |= val << SERDES_MUX_LANE_C_SHIFT; 1334f1d1b7dSMingkai Hu break; 1344f1d1b7dSMingkai Hu case 0xd: 1354f1d1b7dSMingkai Hu reg &= ~SERDES_MUX_LANE_D_MASK; 1364f1d1b7dSMingkai Hu reg |= val << SERDES_MUX_LANE_D_SHIFT; 1374f1d1b7dSMingkai Hu break; 1384f1d1b7dSMingkai Hu default: 1394f1d1b7dSMingkai Hu printf("Invalid value\n"); 1404f1d1b7dSMingkai Hu break; 1414f1d1b7dSMingkai Hu } 1424f1d1b7dSMingkai Hu 1434f1d1b7dSMingkai Hu CPLD_WRITE(serdes_mux, reg); 1444f1d1b7dSMingkai Hu #ifdef DEBUG 1454f1d1b7dSMingkai Hu } else if (strcmp(argv[1], "dump") == 0) { 1464f1d1b7dSMingkai Hu cpld_dump_regs(); 1474f1d1b7dSMingkai Hu #endif 1484f1d1b7dSMingkai Hu } else 1494f1d1b7dSMingkai Hu rc = cmd_usage(cmdtp); 1504f1d1b7dSMingkai Hu 1514f1d1b7dSMingkai Hu return rc; 1524f1d1b7dSMingkai Hu } 1534f1d1b7dSMingkai Hu 1544f1d1b7dSMingkai Hu U_BOOT_CMD( 1554f1d1b7dSMingkai Hu cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, 1564f1d1b7dSMingkai Hu "Reset the board or pin mulexing selection using the CPLD sequencer", 1574f1d1b7dSMingkai Hu "reset - hard reset to default bank\n" 1584f1d1b7dSMingkai Hu "cpld_cmd reset altbank - reset to alternate bank\n" 1594f1d1b7dSMingkai Hu "cpld_cmd watchdog <watchdog_period> - set the watchdog period\n" 1604f1d1b7dSMingkai Hu " period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n" 1614f1d1b7dSMingkai Hu "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n" 162*60820457SShaohui Xie " lane 6: 0 -> slot1\n" 163*60820457SShaohui Xie " 1 -> SGMII (Default)\n" 164*60820457SShaohui Xie " lane a: 0 -> slot2\n" 165*60820457SShaohui Xie " 1 -> AURORA (Default)\n" 166*60820457SShaohui Xie " lane c: 0 -> slot2\n" 167*60820457SShaohui Xie " 1 -> SATA0 (Default)\n" 168*60820457SShaohui Xie " lane d: 0 -> slot2\n" 169*60820457SShaohui Xie " 1 -> SATA1 (Default)\n" 1704f1d1b7dSMingkai Hu #ifdef DEBUG 1714f1d1b7dSMingkai Hu "cpld_cmd dump - display the CPLD registers\n" 1724f1d1b7dSMingkai Hu #endif 1734f1d1b7dSMingkai Hu ); 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