1Overview 2========= 3The P2041 Processor combines four Power Architecture processor cores 4with high-performance datapath acceleration architecture(DPAA), CoreNet 5fabric infrastructure, as well as network and peripheral bus interfaces 6required for networking, telecom/datacom, wireless infrastructure, and 7military/aerospace applications. 8 9P2041RDB board is a quad core platform supporting the P2041 processor 10of QorIQ DPAA series. 11 12Boot from NOR flash 13=================== 141. Build image 15 make P2041RDB_config 16 make all 17 182. Program image 19 => tftp 1000000 u-boot.bin 20 => protect off all 21 => erase eff80000 efffffff 22 => cp.b 1000000 eff80000 80000 23 243. Program RCW 25 => tftp 1000000 rcw.bin 26 => protect off all 27 => erase e8000000 e801ffff 28 => cp.b 1000000 e8000000 50 29 304. Program FMAN Firmware ucode 31 => tftp 1000000 ucode.bin 32 => protect off all 33 => erase ef000000 ef0fffff 34 => cp.b 1000000 ef000000 2000 35 365. Change DIP-switch 37 SW1[1-5] = 10110 38 Note: 1 stands for 'on', 0 stands for 'off' 39 40Boot from SDCard 41=================== 421. Build image 43 make P2041RDB_SDCARD_config 44 make all 45 462. Generate PBL imge 47 Use PE tool to produce a image used to be programed to 48 SDCard which contains RCW and U-Boot image. 49 503. Program the PBL image to SDCard 51 => tftp 1000000 pbl_sd.bin 52 => mmcinfo 53 => mmc write 1000000 8 441 54 554. Program FMAN Firmware ucode 56 => tftp 1000000 ucode.bin 57 => mmc write 1000000 46a 10 58 595. Change DIP-switch 60 SW1[1-5] = 01100 61 Note: 1 stands for 'on', 0 stands for 'off' 62 63Boot from SPI flash 64=================== 651. Build image 66 make P2041RDB_SPIFLASH_config 67 make all 68 692. Generate PBL imge 70 Use PE tool to produce a image used to be programed to 71 SPI flash which contains RCW and U-Boot image. 72 733. Program the PBL image to SPI flash 74 => tftp 1000000 pbl_spi.bin 75 => spi probe 0 76 => sf erase 0 100000 77 => sf write 1000000 0 $filesize 78 794. Program FMAN Firmware ucode 80 => tftp 1000000 ucode.bin 81 => sf erase 110000 10000 82 => sf write 1000000 110000 $filesize 83 845. Change DIP-switch 85 SW1[1-5] = 10100 86 Note: 1 stands for 'on', 0 stands for 'off' 87 88CPLD command 89============ 90The CPLD is used to control the power sequence and some serdes lane 91mux function. 92 93cpld reset - hard reset to default bank 94cpld reset altbank - reset to alternate bank 95cpld lane_mux <lane> <mux_value> - set multiplexed lane pin 96 lane 6: 0 -> slot1 (Default) 97 1 -> SGMII 98 lane a: 0 -> slot2 (Default) 99 1 -> AURORA 100 lane c: 0 -> slot2 (Default) 101 1 -> SATA0 102 lane d: 0 -> slot2 (Default) 103 1 -> SATA1 104 105Using the Device Tree Source File 106================================= 107To create the DTB (Device Tree Binary) image file, use a command 108similar to this: 109 dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb 110 111Or use the following command: 112 {linux-2.6}/make p2041rdb.dtb ARCH=powerpc 113 114then the dtb file will be generated under the following directory: 115 {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb 116 117Booting Linux 118============= 119Place a linux uImage in the TFTP disk area. 120 tftp 1000000 uImage 121 tftp 2000000 rootfs.ext2.gz.uboot 122 tftp 3000000 p2041rdb.dtb 123 bootm 1000000 2000000 3000000 124