1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/mmu.h> 9 10 struct fsl_e_tlb_entry tlb_table[] = { 11 /* TLB 0 - for temp stack in cache */ 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14 MAS3_SX|MAS3_SW|MAS3_SR, 0, 15 0, 0, BOOKE_PAGESZ_4K, 0), 16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 17 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18 MAS3_SX|MAS3_SW|MAS3_SR, 0, 19 0, 0, BOOKE_PAGESZ_4K, 0), 20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 21 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22 MAS3_SX|MAS3_SW|MAS3_SR, 0, 23 0, 0, BOOKE_PAGESZ_4K, 0), 24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 25 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26 MAS3_SX|MAS3_SW|MAS3_SR, 0, 27 0, 0, BOOKE_PAGESZ_4K, 0), 28 29 /* TLB 1 */ 30 /* *I*** - Covers boot page */ 31 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 32 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 33 0, 0, BOOKE_PAGESZ_4K, 1), 34 35 /* *I*G* - CCSRBAR */ 36 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 37 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 38 0, 1, BOOKE_PAGESZ_1M, 1), 39 40 #ifndef CONFIG_SPL_BUILD 41 /* W**G* - Flash, localbus */ 42 /* This will be changed to *I*G* after relocation to RAM. */ 43 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 44 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 45 0, 2, BOOKE_PAGESZ_64M, 1), 46 47 /* W**G* - Flash, localbus */ 48 /* This will be changed to *I*G* after relocation to RAM. */ 49 SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS, 50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51 0, 5, BOOKE_PAGESZ_1M, 1), 52 53 #ifdef CONFIG_PCI 54 /* *I*G* - PCI memory 1.5G */ 55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 56 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57 0, 3, BOOKE_PAGESZ_1G, 1), 58 59 /* *I*G* - PCI I/O effective: 192K */ 60 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 61 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62 0, 4, BOOKE_PAGESZ_256K, 1), 63 #endif 64 65 #endif 66 67 #ifdef CONFIG_SYS_RAMBOOT 68 /* *I*G - eSDHC boot */ 69 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 71 0, 8, BOOKE_PAGESZ_1G, 1), 72 #endif 73 74 }; 75 76 int num_tlb_entries = ARRAY_SIZE(tlb_table); 77