1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <hwconfig.h> 26 #include <pci.h> 27 #include <i2c.h> 28 #include <asm/processor.h> 29 #include <asm/mmu.h> 30 #include <asm/cache.h> 31 #include <asm/immap_85xx.h> 32 #include <asm/fsl_pci.h> 33 #include <asm/fsl_ddr_sdram.h> 34 #include <asm/io.h> 35 #include <asm/fsl_law.h> 36 #include <asm/fsl_lbc.h> 37 #include <asm/mp.h> 38 #include <miiphy.h> 39 #include <libfdt.h> 40 #include <fdt_support.h> 41 #include <fsl_mdio.h> 42 #include <tsec.h> 43 #include <ioports.h> 44 #include <asm/fsl_serdes.h> 45 #include <netdev.h> 46 47 #define SYSCLK_64 64000000 48 #define SYSCLK_66 66666666 49 50 unsigned long get_board_sys_clk(ulong dummy) 51 { 52 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 53 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); 54 unsigned int cpdat_val = 0; 55 56 /* Set-up up pin muxing based on board switch settings */ 57 cpdat_val = par_io[1].cpdat; 58 59 /* Check switch setting for SYSCLK select (PB3) */ 60 if (cpdat_val & 0x10000000) 61 return SYSCLK_64; 62 else 63 return SYSCLK_66; 64 65 return 0; 66 } 67 68 #ifdef CONFIG_QE 69 70 #define PCA_IOPORT_I2C_ADDR 0x23 71 #define PCA_IOPORT_OUTPUT_CMD 0x2 72 #define PCA_IOPORT_CFG_CMD 0x6 73 74 const qe_iop_conf_t qe_iop_conf_tab[] = { 75 76 #ifdef CONFIG_TWR_P1025 77 /* GPIO */ 78 {1, 0, 1, 0, 0}, 79 {1, 18, 1, 0, 0}, 80 81 /* GPIO for switch options */ 82 {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */ 83 {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */ 84 {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */ 85 {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */ 86 87 /* QE_MUX_MDC */ 88 {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ 89 90 /* QE_MUX_MDIO */ 91 {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ 92 93 /* UCC_1_MII */ 94 {0, 23, 2, 0, 2}, /* CLK12 */ 95 {0, 24, 2, 0, 1}, /* CLK9 */ 96 {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ 97 {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ 98 {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ 99 {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ 100 {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ 101 {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ 102 {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ 103 {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ 104 {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 105 {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ 106 {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ 107 {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ 108 {0, 17, 2, 0, 2}, /* ENET1_CRS */ 109 {0, 16, 2, 0, 2}, /* ENET1_COL */ 110 111 /* UCC_5_RMII */ 112 {1, 11, 2, 0, 1}, /* CLK13 */ 113 {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ 114 {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ 115 {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ 116 {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ 117 {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ 118 {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ 119 {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ 120 121 /* TDMA - clock option is configured in OS based on board setting */ 122 {1, 23, 2, 0, 2}, /* TDMA_TXD */ 123 {1, 25, 2, 0, 2}, /* TDMA_RXD */ 124 {1, 26, 1, 0, 2}, /* TDMA_SYNC */ 125 #endif 126 127 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 128 }; 129 #endif 130 131 int board_early_init_f(void) 132 { 133 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 134 135 setbits_be32(&gur->pmuxcr, 136 (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); 137 138 /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */ 139 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); 140 141 return 0; 142 } 143 144 int checkboard(void) 145 { 146 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 147 u8 boot_status; 148 149 printf("Board: %s\n", CONFIG_BOARDNAME); 150 151 boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 152 puts("rom_loc: "); 153 if (boot_status == PORBMSR_ROMLOC_NOR) 154 puts("nor flash"); 155 else if (boot_status == PORBMSR_ROMLOC_SDHC) 156 puts("sd"); 157 else 158 puts("unknown"); 159 puts("\n"); 160 161 return 0; 162 } 163 164 #ifdef CONFIG_PCI 165 void pci_init_board(void) 166 { 167 fsl_pcie_init_board(0); 168 } 169 #endif 170 171 int board_early_init_r(void) 172 { 173 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 174 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 175 176 /* 177 * Remap Boot flash region to caching-inhibited 178 * so that flash can be erased properly. 179 */ 180 181 /* Flush d-cache and invalidate i-cache of any FLASH data */ 182 flush_dcache(); 183 invalidate_icache(); 184 185 /* invalidate existing TLB entry for flash */ 186 disable_tlb(flash_esel); 187 188 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 189 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 190 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ 191 return 0; 192 } 193 194 int board_eth_init(bd_t *bis) 195 { 196 struct fsl_pq_mdio_info mdio_info; 197 struct tsec_info_struct tsec_info[4]; 198 ccsr_gur_t *gur __attribute__((unused)) = 199 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 200 int num = 0; 201 202 #ifdef CONFIG_TSEC1 203 SET_STD_TSEC_INFO(tsec_info[num], 1); 204 num++; 205 #endif 206 #ifdef CONFIG_TSEC2 207 SET_STD_TSEC_INFO(tsec_info[num], 2); 208 if (is_serdes_configured(SGMII_TSEC2)) { 209 printf("eTSEC2 is in sgmii mode.\n"); 210 tsec_info[num].flags |= TSEC_SGMII; 211 } 212 num++; 213 #endif 214 #ifdef CONFIG_TSEC3 215 SET_STD_TSEC_INFO(tsec_info[num], 3); 216 num++; 217 #endif 218 219 if (!num) { 220 printf("No TSECs initialized\n"); 221 return 0; 222 } 223 224 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 225 mdio_info.name = DEFAULT_MII_NAME; 226 227 fsl_pq_mdio_init(bis, &mdio_info); 228 229 tsec_eth_init(bis, tsec_info, num); 230 231 #if defined(CONFIG_UEC_ETH) 232 /* QE0 and QE3 need to be exposed for UCC1 233 * and UCC5 Eth mode (in PMUXCR register). 234 * Currently QE/LBC muxed pins assumed to be 235 * LBC for U-Boot and PMUXCR updated by OS if required */ 236 237 uec_standard_init(bis); 238 #endif 239 240 return pci_eth_init(bis); 241 } 242 243 #if defined(CONFIG_QE) 244 static void fdt_board_fixup_qe_pins(void *blob) 245 { 246 int node; 247 248 if (!hwconfig("qe")) { 249 /* For QE and eLBC pins multiplexing, 250 * When don't use QE function, remove 251 * qe node from dt blob. 252 */ 253 node = fdt_path_offset(blob, "/qe"); 254 if (node >= 0) 255 fdt_del_node(blob, node); 256 } else { 257 /* For TWR Peripheral Modules - TWR-SER2 258 * board only can support Signal Port MII, 259 * so delete one UEC node when use MII port. 260 */ 261 if (hwconfig("mii")) 262 node = fdt_path_offset(blob, "/qe/ucc@2400"); 263 else 264 node = fdt_path_offset(blob, "/qe/ucc@2000"); 265 if (node >= 0) 266 fdt_del_node(blob, node); 267 } 268 269 return; 270 } 271 #endif 272 273 #ifdef CONFIG_OF_BOARD_SETUP 274 void ft_board_setup(void *blob, bd_t *bd) 275 { 276 phys_addr_t base; 277 phys_size_t size; 278 279 ft_cpu_setup(blob, bd); 280 281 base = getenv_bootm_low(); 282 size = getenv_bootm_size(); 283 284 fdt_fixup_memory(blob, (u64)base, (u64)size); 285 286 FT_FSL_PCI_SETUP; 287 288 #ifdef CONFIG_QE 289 do_fixup_by_compat(blob, "fsl,qe", "status", "okay", 290 sizeof("okay"), 0); 291 #endif 292 #if defined(CONFIG_TWR_P1025) 293 fdt_board_fixup_qe_pins(blob); 294 #endif 295 fdt_fixup_dr_usb(blob, bd); 296 } 297 #endif 298