1*49f5befaSXie Xiaobo /* 2*49f5befaSXie Xiaobo * Copyright 2013 Freescale Semiconductor, Inc. 3*49f5befaSXie Xiaobo * 4*49f5befaSXie Xiaobo * See file CREDITS for list of people who contributed to this 5*49f5befaSXie Xiaobo * project. 6*49f5befaSXie Xiaobo * 7*49f5befaSXie Xiaobo * This program is free software; you can redistribute it and/or 8*49f5befaSXie Xiaobo * modify it under the terms of the GNU General Public License as 9*49f5befaSXie Xiaobo * published by the Free Software Foundation; either version 2 of 10*49f5befaSXie Xiaobo * the License, or (at your option) any later version. 11*49f5befaSXie Xiaobo * 12*49f5befaSXie Xiaobo * This program is distributed in the hope that it will be useful, 13*49f5befaSXie Xiaobo * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*49f5befaSXie Xiaobo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*49f5befaSXie Xiaobo * GNU General Public License for more details. 16*49f5befaSXie Xiaobo * 17*49f5befaSXie Xiaobo * You should have received a copy of the GNU General Public License 18*49f5befaSXie Xiaobo * along with this program; if not, write to the Free Software 19*49f5befaSXie Xiaobo * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20*49f5befaSXie Xiaobo * MA 02111-1307 USA 21*49f5befaSXie Xiaobo */ 22*49f5befaSXie Xiaobo 23*49f5befaSXie Xiaobo #include <common.h> 24*49f5befaSXie Xiaobo #include <command.h> 25*49f5befaSXie Xiaobo #include <hwconfig.h> 26*49f5befaSXie Xiaobo #include <pci.h> 27*49f5befaSXie Xiaobo #include <i2c.h> 28*49f5befaSXie Xiaobo #include <asm/processor.h> 29*49f5befaSXie Xiaobo #include <asm/mmu.h> 30*49f5befaSXie Xiaobo #include <asm/cache.h> 31*49f5befaSXie Xiaobo #include <asm/immap_85xx.h> 32*49f5befaSXie Xiaobo #include <asm/fsl_pci.h> 33*49f5befaSXie Xiaobo #include <asm/fsl_ddr_sdram.h> 34*49f5befaSXie Xiaobo #include <asm/io.h> 35*49f5befaSXie Xiaobo #include <asm/fsl_law.h> 36*49f5befaSXie Xiaobo #include <asm/fsl_lbc.h> 37*49f5befaSXie Xiaobo #include <asm/mp.h> 38*49f5befaSXie Xiaobo #include <miiphy.h> 39*49f5befaSXie Xiaobo #include <libfdt.h> 40*49f5befaSXie Xiaobo #include <fdt_support.h> 41*49f5befaSXie Xiaobo #include <fsl_mdio.h> 42*49f5befaSXie Xiaobo #include <tsec.h> 43*49f5befaSXie Xiaobo #include <ioports.h> 44*49f5befaSXie Xiaobo #include <asm/fsl_serdes.h> 45*49f5befaSXie Xiaobo #include <netdev.h> 46*49f5befaSXie Xiaobo 47*49f5befaSXie Xiaobo #define SYSCLK_64 64000000 48*49f5befaSXie Xiaobo #define SYSCLK_66 66666666 49*49f5befaSXie Xiaobo 50*49f5befaSXie Xiaobo unsigned long get_board_sys_clk(ulong dummy) 51*49f5befaSXie Xiaobo { 52*49f5befaSXie Xiaobo ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 53*49f5befaSXie Xiaobo par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); 54*49f5befaSXie Xiaobo unsigned int cpdat_val = 0; 55*49f5befaSXie Xiaobo 56*49f5befaSXie Xiaobo /* Set-up up pin muxing based on board switch settings */ 57*49f5befaSXie Xiaobo cpdat_val = par_io[1].cpdat; 58*49f5befaSXie Xiaobo 59*49f5befaSXie Xiaobo /* Check switch setting for SYSCLK select (PB3) */ 60*49f5befaSXie Xiaobo if (cpdat_val & 0x10000000) 61*49f5befaSXie Xiaobo return SYSCLK_64; 62*49f5befaSXie Xiaobo else 63*49f5befaSXie Xiaobo return SYSCLK_66; 64*49f5befaSXie Xiaobo 65*49f5befaSXie Xiaobo return 0; 66*49f5befaSXie Xiaobo } 67*49f5befaSXie Xiaobo 68*49f5befaSXie Xiaobo #ifdef CONFIG_QE 69*49f5befaSXie Xiaobo 70*49f5befaSXie Xiaobo #define PCA_IOPORT_I2C_ADDR 0x23 71*49f5befaSXie Xiaobo #define PCA_IOPORT_OUTPUT_CMD 0x2 72*49f5befaSXie Xiaobo #define PCA_IOPORT_CFG_CMD 0x6 73*49f5befaSXie Xiaobo 74*49f5befaSXie Xiaobo const qe_iop_conf_t qe_iop_conf_tab[] = { 75*49f5befaSXie Xiaobo 76*49f5befaSXie Xiaobo #ifdef CONFIG_TWR_P1025 77*49f5befaSXie Xiaobo /* GPIO */ 78*49f5befaSXie Xiaobo {1, 0, 1, 0, 0}, 79*49f5befaSXie Xiaobo {1, 18, 1, 0, 0}, 80*49f5befaSXie Xiaobo 81*49f5befaSXie Xiaobo /* GPIO for switch options */ 82*49f5befaSXie Xiaobo {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */ 83*49f5befaSXie Xiaobo {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */ 84*49f5befaSXie Xiaobo {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */ 85*49f5befaSXie Xiaobo {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */ 86*49f5befaSXie Xiaobo 87*49f5befaSXie Xiaobo /* QE_MUX_MDC */ 88*49f5befaSXie Xiaobo {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ 89*49f5befaSXie Xiaobo 90*49f5befaSXie Xiaobo /* QE_MUX_MDIO */ 91*49f5befaSXie Xiaobo {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ 92*49f5befaSXie Xiaobo 93*49f5befaSXie Xiaobo /* UCC_1_MII */ 94*49f5befaSXie Xiaobo {0, 23, 2, 0, 2}, /* CLK12 */ 95*49f5befaSXie Xiaobo {0, 24, 2, 0, 1}, /* CLK9 */ 96*49f5befaSXie Xiaobo {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ 97*49f5befaSXie Xiaobo {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ 98*49f5befaSXie Xiaobo {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ 99*49f5befaSXie Xiaobo {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ 100*49f5befaSXie Xiaobo {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ 101*49f5befaSXie Xiaobo {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ 102*49f5befaSXie Xiaobo {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ 103*49f5befaSXie Xiaobo {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ 104*49f5befaSXie Xiaobo {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 105*49f5befaSXie Xiaobo {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ 106*49f5befaSXie Xiaobo {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ 107*49f5befaSXie Xiaobo {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ 108*49f5befaSXie Xiaobo {0, 17, 2, 0, 2}, /* ENET1_CRS */ 109*49f5befaSXie Xiaobo {0, 16, 2, 0, 2}, /* ENET1_COL */ 110*49f5befaSXie Xiaobo 111*49f5befaSXie Xiaobo /* UCC_5_RMII */ 112*49f5befaSXie Xiaobo {1, 11, 2, 0, 1}, /* CLK13 */ 113*49f5befaSXie Xiaobo {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ 114*49f5befaSXie Xiaobo {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ 115*49f5befaSXie Xiaobo {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ 116*49f5befaSXie Xiaobo {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ 117*49f5befaSXie Xiaobo {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ 118*49f5befaSXie Xiaobo {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ 119*49f5befaSXie Xiaobo {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ 120*49f5befaSXie Xiaobo 121*49f5befaSXie Xiaobo /* TDMA - clock option is configured in OS based on board setting */ 122*49f5befaSXie Xiaobo {1, 23, 2, 0, 2}, /* TDMA_TXD */ 123*49f5befaSXie Xiaobo {1, 25, 2, 0, 2}, /* TDMA_RXD */ 124*49f5befaSXie Xiaobo {1, 26, 1, 0, 2}, /* TDMA_SYNC */ 125*49f5befaSXie Xiaobo #endif 126*49f5befaSXie Xiaobo 127*49f5befaSXie Xiaobo {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 128*49f5befaSXie Xiaobo }; 129*49f5befaSXie Xiaobo #endif 130*49f5befaSXie Xiaobo 131*49f5befaSXie Xiaobo int board_early_init_f(void) 132*49f5befaSXie Xiaobo { 133*49f5befaSXie Xiaobo ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 134*49f5befaSXie Xiaobo 135*49f5befaSXie Xiaobo setbits_be32(&gur->pmuxcr, 136*49f5befaSXie Xiaobo (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); 137*49f5befaSXie Xiaobo 138*49f5befaSXie Xiaobo /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */ 139*49f5befaSXie Xiaobo clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); 140*49f5befaSXie Xiaobo 141*49f5befaSXie Xiaobo return 0; 142*49f5befaSXie Xiaobo } 143*49f5befaSXie Xiaobo 144*49f5befaSXie Xiaobo int checkboard(void) 145*49f5befaSXie Xiaobo { 146*49f5befaSXie Xiaobo ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 147*49f5befaSXie Xiaobo u8 boot_status; 148*49f5befaSXie Xiaobo 149*49f5befaSXie Xiaobo printf("Board: %s\n", CONFIG_BOARDNAME); 150*49f5befaSXie Xiaobo 151*49f5befaSXie Xiaobo boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 152*49f5befaSXie Xiaobo puts("rom_loc: "); 153*49f5befaSXie Xiaobo if (boot_status == PORBMSR_ROMLOC_NOR) 154*49f5befaSXie Xiaobo puts("nor flash"); 155*49f5befaSXie Xiaobo else if (boot_status == PORBMSR_ROMLOC_SDHC) 156*49f5befaSXie Xiaobo puts("sd"); 157*49f5befaSXie Xiaobo else 158*49f5befaSXie Xiaobo puts("unknown"); 159*49f5befaSXie Xiaobo puts("\n"); 160*49f5befaSXie Xiaobo 161*49f5befaSXie Xiaobo return 0; 162*49f5befaSXie Xiaobo } 163*49f5befaSXie Xiaobo 164*49f5befaSXie Xiaobo #ifdef CONFIG_PCI 165*49f5befaSXie Xiaobo void pci_init_board(void) 166*49f5befaSXie Xiaobo { 167*49f5befaSXie Xiaobo fsl_pcie_init_board(0); 168*49f5befaSXie Xiaobo } 169*49f5befaSXie Xiaobo #endif 170*49f5befaSXie Xiaobo 171*49f5befaSXie Xiaobo int board_early_init_r(void) 172*49f5befaSXie Xiaobo { 173*49f5befaSXie Xiaobo const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 174*49f5befaSXie Xiaobo const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 175*49f5befaSXie Xiaobo 176*49f5befaSXie Xiaobo /* 177*49f5befaSXie Xiaobo * Remap Boot flash region to caching-inhibited 178*49f5befaSXie Xiaobo * so that flash can be erased properly. 179*49f5befaSXie Xiaobo */ 180*49f5befaSXie Xiaobo 181*49f5befaSXie Xiaobo /* Flush d-cache and invalidate i-cache of any FLASH data */ 182*49f5befaSXie Xiaobo flush_dcache(); 183*49f5befaSXie Xiaobo invalidate_icache(); 184*49f5befaSXie Xiaobo 185*49f5befaSXie Xiaobo /* invalidate existing TLB entry for flash */ 186*49f5befaSXie Xiaobo disable_tlb(flash_esel); 187*49f5befaSXie Xiaobo 188*49f5befaSXie Xiaobo set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 189*49f5befaSXie Xiaobo MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 190*49f5befaSXie Xiaobo 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ 191*49f5befaSXie Xiaobo return 0; 192*49f5befaSXie Xiaobo } 193*49f5befaSXie Xiaobo 194*49f5befaSXie Xiaobo int board_eth_init(bd_t *bis) 195*49f5befaSXie Xiaobo { 196*49f5befaSXie Xiaobo struct fsl_pq_mdio_info mdio_info; 197*49f5befaSXie Xiaobo struct tsec_info_struct tsec_info[4]; 198*49f5befaSXie Xiaobo ccsr_gur_t *gur __attribute__((unused)) = 199*49f5befaSXie Xiaobo (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 200*49f5befaSXie Xiaobo int num = 0; 201*49f5befaSXie Xiaobo 202*49f5befaSXie Xiaobo #ifdef CONFIG_TSEC1 203*49f5befaSXie Xiaobo SET_STD_TSEC_INFO(tsec_info[num], 1); 204*49f5befaSXie Xiaobo num++; 205*49f5befaSXie Xiaobo #endif 206*49f5befaSXie Xiaobo #ifdef CONFIG_TSEC2 207*49f5befaSXie Xiaobo SET_STD_TSEC_INFO(tsec_info[num], 2); 208*49f5befaSXie Xiaobo if (is_serdes_configured(SGMII_TSEC2)) { 209*49f5befaSXie Xiaobo printf("eTSEC2 is in sgmii mode.\n"); 210*49f5befaSXie Xiaobo tsec_info[num].flags |= TSEC_SGMII; 211*49f5befaSXie Xiaobo } 212*49f5befaSXie Xiaobo num++; 213*49f5befaSXie Xiaobo #endif 214*49f5befaSXie Xiaobo #ifdef CONFIG_TSEC3 215*49f5befaSXie Xiaobo SET_STD_TSEC_INFO(tsec_info[num], 3); 216*49f5befaSXie Xiaobo num++; 217*49f5befaSXie Xiaobo #endif 218*49f5befaSXie Xiaobo 219*49f5befaSXie Xiaobo if (!num) { 220*49f5befaSXie Xiaobo printf("No TSECs initialized\n"); 221*49f5befaSXie Xiaobo return 0; 222*49f5befaSXie Xiaobo } 223*49f5befaSXie Xiaobo 224*49f5befaSXie Xiaobo mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 225*49f5befaSXie Xiaobo mdio_info.name = DEFAULT_MII_NAME; 226*49f5befaSXie Xiaobo 227*49f5befaSXie Xiaobo fsl_pq_mdio_init(bis, &mdio_info); 228*49f5befaSXie Xiaobo 229*49f5befaSXie Xiaobo tsec_eth_init(bis, tsec_info, num); 230*49f5befaSXie Xiaobo 231*49f5befaSXie Xiaobo #if defined(CONFIG_UEC_ETH) 232*49f5befaSXie Xiaobo /* QE0 and QE3 need to be exposed for UCC1 233*49f5befaSXie Xiaobo * and UCC5 Eth mode (in PMUXCR register). 234*49f5befaSXie Xiaobo * Currently QE/LBC muxed pins assumed to be 235*49f5befaSXie Xiaobo * LBC for U-Boot and PMUXCR updated by OS if required */ 236*49f5befaSXie Xiaobo 237*49f5befaSXie Xiaobo uec_standard_init(bis); 238*49f5befaSXie Xiaobo #endif 239*49f5befaSXie Xiaobo 240*49f5befaSXie Xiaobo return pci_eth_init(bis); 241*49f5befaSXie Xiaobo } 242*49f5befaSXie Xiaobo 243*49f5befaSXie Xiaobo #if defined(CONFIG_QE) 244*49f5befaSXie Xiaobo static void fdt_board_fixup_qe_pins(void *blob) 245*49f5befaSXie Xiaobo { 246*49f5befaSXie Xiaobo int node; 247*49f5befaSXie Xiaobo 248*49f5befaSXie Xiaobo if (!hwconfig("qe")) { 249*49f5befaSXie Xiaobo /* For QE and eLBC pins multiplexing, 250*49f5befaSXie Xiaobo * When don't use QE function, remove 251*49f5befaSXie Xiaobo * qe node from dt blob. 252*49f5befaSXie Xiaobo */ 253*49f5befaSXie Xiaobo node = fdt_path_offset(blob, "/qe"); 254*49f5befaSXie Xiaobo if (node >= 0) 255*49f5befaSXie Xiaobo fdt_del_node(blob, node); 256*49f5befaSXie Xiaobo } else { 257*49f5befaSXie Xiaobo /* For TWR Peripheral Modules - TWR-SER2 258*49f5befaSXie Xiaobo * board only can support Signal Port MII, 259*49f5befaSXie Xiaobo * so delete one UEC node when use MII port. 260*49f5befaSXie Xiaobo */ 261*49f5befaSXie Xiaobo if (hwconfig("mii")) 262*49f5befaSXie Xiaobo node = fdt_path_offset(blob, "/qe/ucc@2400"); 263*49f5befaSXie Xiaobo else 264*49f5befaSXie Xiaobo node = fdt_path_offset(blob, "/qe/ucc@2000"); 265*49f5befaSXie Xiaobo if (node >= 0) 266*49f5befaSXie Xiaobo fdt_del_node(blob, node); 267*49f5befaSXie Xiaobo } 268*49f5befaSXie Xiaobo 269*49f5befaSXie Xiaobo return; 270*49f5befaSXie Xiaobo } 271*49f5befaSXie Xiaobo #endif 272*49f5befaSXie Xiaobo 273*49f5befaSXie Xiaobo #ifdef CONFIG_OF_BOARD_SETUP 274*49f5befaSXie Xiaobo void ft_board_setup(void *blob, bd_t *bd) 275*49f5befaSXie Xiaobo { 276*49f5befaSXie Xiaobo phys_addr_t base; 277*49f5befaSXie Xiaobo phys_size_t size; 278*49f5befaSXie Xiaobo 279*49f5befaSXie Xiaobo ft_cpu_setup(blob, bd); 280*49f5befaSXie Xiaobo 281*49f5befaSXie Xiaobo base = getenv_bootm_low(); 282*49f5befaSXie Xiaobo size = getenv_bootm_size(); 283*49f5befaSXie Xiaobo 284*49f5befaSXie Xiaobo fdt_fixup_memory(blob, (u64)base, (u64)size); 285*49f5befaSXie Xiaobo 286*49f5befaSXie Xiaobo FT_FSL_PCI_SETUP; 287*49f5befaSXie Xiaobo 288*49f5befaSXie Xiaobo #ifdef CONFIG_QE 289*49f5befaSXie Xiaobo do_fixup_by_compat(blob, "fsl,qe", "status", "okay", 290*49f5befaSXie Xiaobo sizeof("okay"), 0); 291*49f5befaSXie Xiaobo #endif 292*49f5befaSXie Xiaobo #if defined(CONFIG_TWR_P1025) 293*49f5befaSXie Xiaobo fdt_board_fixup_qe_pins(blob); 294*49f5befaSXie Xiaobo #endif 295*49f5befaSXie Xiaobo fdt_fixup_dr_usb(blob, bd); 296*49f5befaSXie Xiaobo } 297*49f5befaSXie Xiaobo #endif 298