149f5befaSXie Xiaobo /* 249f5befaSXie Xiaobo * Copyright 2013 Freescale Semiconductor, Inc. 349f5befaSXie Xiaobo * 4*3aab0cd8SYork Sun * SPDX-License-Identifier: GPL-2.0+ 549f5befaSXie Xiaobo */ 649f5befaSXie Xiaobo 749f5befaSXie Xiaobo #include <common.h> 849f5befaSXie Xiaobo #include <command.h> 949f5befaSXie Xiaobo #include <hwconfig.h> 1049f5befaSXie Xiaobo #include <pci.h> 1149f5befaSXie Xiaobo #include <i2c.h> 1249f5befaSXie Xiaobo #include <asm/processor.h> 1349f5befaSXie Xiaobo #include <asm/mmu.h> 1449f5befaSXie Xiaobo #include <asm/cache.h> 1549f5befaSXie Xiaobo #include <asm/immap_85xx.h> 1649f5befaSXie Xiaobo #include <asm/fsl_pci.h> 1749f5befaSXie Xiaobo #include <asm/fsl_ddr_sdram.h> 1849f5befaSXie Xiaobo #include <asm/io.h> 1949f5befaSXie Xiaobo #include <asm/fsl_law.h> 2049f5befaSXie Xiaobo #include <asm/fsl_lbc.h> 2149f5befaSXie Xiaobo #include <asm/mp.h> 2249f5befaSXie Xiaobo #include <miiphy.h> 2349f5befaSXie Xiaobo #include <libfdt.h> 2449f5befaSXie Xiaobo #include <fdt_support.h> 2549f5befaSXie Xiaobo #include <fsl_mdio.h> 2649f5befaSXie Xiaobo #include <tsec.h> 2749f5befaSXie Xiaobo #include <ioports.h> 2849f5befaSXie Xiaobo #include <asm/fsl_serdes.h> 2949f5befaSXie Xiaobo #include <netdev.h> 3049f5befaSXie Xiaobo 3149f5befaSXie Xiaobo #define SYSCLK_64 64000000 3249f5befaSXie Xiaobo #define SYSCLK_66 66666666 3349f5befaSXie Xiaobo 3449f5befaSXie Xiaobo unsigned long get_board_sys_clk(ulong dummy) 3549f5befaSXie Xiaobo { 3649f5befaSXie Xiaobo ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 3749f5befaSXie Xiaobo par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); 3849f5befaSXie Xiaobo unsigned int cpdat_val = 0; 3949f5befaSXie Xiaobo 4049f5befaSXie Xiaobo /* Set-up up pin muxing based on board switch settings */ 4149f5befaSXie Xiaobo cpdat_val = par_io[1].cpdat; 4249f5befaSXie Xiaobo 4349f5befaSXie Xiaobo /* Check switch setting for SYSCLK select (PB3) */ 4449f5befaSXie Xiaobo if (cpdat_val & 0x10000000) 4549f5befaSXie Xiaobo return SYSCLK_64; 4649f5befaSXie Xiaobo else 4749f5befaSXie Xiaobo return SYSCLK_66; 4849f5befaSXie Xiaobo 4949f5befaSXie Xiaobo return 0; 5049f5befaSXie Xiaobo } 5149f5befaSXie Xiaobo 5249f5befaSXie Xiaobo #ifdef CONFIG_QE 5349f5befaSXie Xiaobo 5449f5befaSXie Xiaobo #define PCA_IOPORT_I2C_ADDR 0x23 5549f5befaSXie Xiaobo #define PCA_IOPORT_OUTPUT_CMD 0x2 5649f5befaSXie Xiaobo #define PCA_IOPORT_CFG_CMD 0x6 5749f5befaSXie Xiaobo 5849f5befaSXie Xiaobo const qe_iop_conf_t qe_iop_conf_tab[] = { 5949f5befaSXie Xiaobo 6049f5befaSXie Xiaobo #ifdef CONFIG_TWR_P1025 6149f5befaSXie Xiaobo /* GPIO */ 6249f5befaSXie Xiaobo {1, 0, 1, 0, 0}, 6349f5befaSXie Xiaobo {1, 18, 1, 0, 0}, 6449f5befaSXie Xiaobo 6549f5befaSXie Xiaobo /* GPIO for switch options */ 6649f5befaSXie Xiaobo {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */ 6749f5befaSXie Xiaobo {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */ 6849f5befaSXie Xiaobo {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */ 6949f5befaSXie Xiaobo {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */ 7049f5befaSXie Xiaobo 7149f5befaSXie Xiaobo /* QE_MUX_MDC */ 7249f5befaSXie Xiaobo {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ 7349f5befaSXie Xiaobo 7449f5befaSXie Xiaobo /* QE_MUX_MDIO */ 7549f5befaSXie Xiaobo {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ 7649f5befaSXie Xiaobo 7749f5befaSXie Xiaobo /* UCC_1_MII */ 7849f5befaSXie Xiaobo {0, 23, 2, 0, 2}, /* CLK12 */ 7949f5befaSXie Xiaobo {0, 24, 2, 0, 1}, /* CLK9 */ 8049f5befaSXie Xiaobo {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ 8149f5befaSXie Xiaobo {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ 8249f5befaSXie Xiaobo {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ 8349f5befaSXie Xiaobo {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ 8449f5befaSXie Xiaobo {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ 8549f5befaSXie Xiaobo {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ 8649f5befaSXie Xiaobo {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ 8749f5befaSXie Xiaobo {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ 8849f5befaSXie Xiaobo {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 8949f5befaSXie Xiaobo {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ 9049f5befaSXie Xiaobo {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ 9149f5befaSXie Xiaobo {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ 9249f5befaSXie Xiaobo {0, 17, 2, 0, 2}, /* ENET1_CRS */ 9349f5befaSXie Xiaobo {0, 16, 2, 0, 2}, /* ENET1_COL */ 9449f5befaSXie Xiaobo 9549f5befaSXie Xiaobo /* UCC_5_RMII */ 9649f5befaSXie Xiaobo {1, 11, 2, 0, 1}, /* CLK13 */ 9749f5befaSXie Xiaobo {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ 9849f5befaSXie Xiaobo {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ 9949f5befaSXie Xiaobo {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ 10049f5befaSXie Xiaobo {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ 10149f5befaSXie Xiaobo {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ 10249f5befaSXie Xiaobo {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ 10349f5befaSXie Xiaobo {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ 10449f5befaSXie Xiaobo 10549f5befaSXie Xiaobo /* TDMA - clock option is configured in OS based on board setting */ 10649f5befaSXie Xiaobo {1, 23, 2, 0, 2}, /* TDMA_TXD */ 10749f5befaSXie Xiaobo {1, 25, 2, 0, 2}, /* TDMA_RXD */ 10849f5befaSXie Xiaobo {1, 26, 1, 0, 2}, /* TDMA_SYNC */ 10949f5befaSXie Xiaobo #endif 11049f5befaSXie Xiaobo 11149f5befaSXie Xiaobo {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 11249f5befaSXie Xiaobo }; 11349f5befaSXie Xiaobo #endif 11449f5befaSXie Xiaobo 11549f5befaSXie Xiaobo int board_early_init_f(void) 11649f5befaSXie Xiaobo { 11749f5befaSXie Xiaobo ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 11849f5befaSXie Xiaobo 11949f5befaSXie Xiaobo setbits_be32(&gur->pmuxcr, 12049f5befaSXie Xiaobo (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); 12149f5befaSXie Xiaobo 12249f5befaSXie Xiaobo /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */ 12349f5befaSXie Xiaobo clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); 12449f5befaSXie Xiaobo 12549f5befaSXie Xiaobo return 0; 12649f5befaSXie Xiaobo } 12749f5befaSXie Xiaobo 12849f5befaSXie Xiaobo int checkboard(void) 12949f5befaSXie Xiaobo { 13049f5befaSXie Xiaobo ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 13149f5befaSXie Xiaobo u8 boot_status; 13249f5befaSXie Xiaobo 13349f5befaSXie Xiaobo printf("Board: %s\n", CONFIG_BOARDNAME); 13449f5befaSXie Xiaobo 13549f5befaSXie Xiaobo boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 13649f5befaSXie Xiaobo puts("rom_loc: "); 13749f5befaSXie Xiaobo if (boot_status == PORBMSR_ROMLOC_NOR) 13849f5befaSXie Xiaobo puts("nor flash"); 13949f5befaSXie Xiaobo else if (boot_status == PORBMSR_ROMLOC_SDHC) 14049f5befaSXie Xiaobo puts("sd"); 14149f5befaSXie Xiaobo else 14249f5befaSXie Xiaobo puts("unknown"); 14349f5befaSXie Xiaobo puts("\n"); 14449f5befaSXie Xiaobo 14549f5befaSXie Xiaobo return 0; 14649f5befaSXie Xiaobo } 14749f5befaSXie Xiaobo 14849f5befaSXie Xiaobo #ifdef CONFIG_PCI 14949f5befaSXie Xiaobo void pci_init_board(void) 15049f5befaSXie Xiaobo { 15149f5befaSXie Xiaobo fsl_pcie_init_board(0); 15249f5befaSXie Xiaobo } 15349f5befaSXie Xiaobo #endif 15449f5befaSXie Xiaobo 15549f5befaSXie Xiaobo int board_early_init_r(void) 15649f5befaSXie Xiaobo { 15749f5befaSXie Xiaobo const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 15849f5befaSXie Xiaobo const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 15949f5befaSXie Xiaobo 16049f5befaSXie Xiaobo /* 16149f5befaSXie Xiaobo * Remap Boot flash region to caching-inhibited 16249f5befaSXie Xiaobo * so that flash can be erased properly. 16349f5befaSXie Xiaobo */ 16449f5befaSXie Xiaobo 16549f5befaSXie Xiaobo /* Flush d-cache and invalidate i-cache of any FLASH data */ 16649f5befaSXie Xiaobo flush_dcache(); 16749f5befaSXie Xiaobo invalidate_icache(); 16849f5befaSXie Xiaobo 16949f5befaSXie Xiaobo /* invalidate existing TLB entry for flash */ 17049f5befaSXie Xiaobo disable_tlb(flash_esel); 17149f5befaSXie Xiaobo 17249f5befaSXie Xiaobo set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 17349f5befaSXie Xiaobo MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 17449f5befaSXie Xiaobo 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ 17549f5befaSXie Xiaobo return 0; 17649f5befaSXie Xiaobo } 17749f5befaSXie Xiaobo 17849f5befaSXie Xiaobo int board_eth_init(bd_t *bis) 17949f5befaSXie Xiaobo { 18049f5befaSXie Xiaobo struct fsl_pq_mdio_info mdio_info; 18149f5befaSXie Xiaobo struct tsec_info_struct tsec_info[4]; 18249f5befaSXie Xiaobo ccsr_gur_t *gur __attribute__((unused)) = 18349f5befaSXie Xiaobo (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 18449f5befaSXie Xiaobo int num = 0; 18549f5befaSXie Xiaobo 18649f5befaSXie Xiaobo #ifdef CONFIG_TSEC1 18749f5befaSXie Xiaobo SET_STD_TSEC_INFO(tsec_info[num], 1); 18849f5befaSXie Xiaobo num++; 18949f5befaSXie Xiaobo #endif 19049f5befaSXie Xiaobo #ifdef CONFIG_TSEC2 19149f5befaSXie Xiaobo SET_STD_TSEC_INFO(tsec_info[num], 2); 19249f5befaSXie Xiaobo if (is_serdes_configured(SGMII_TSEC2)) { 19349f5befaSXie Xiaobo printf("eTSEC2 is in sgmii mode.\n"); 19449f5befaSXie Xiaobo tsec_info[num].flags |= TSEC_SGMII; 19549f5befaSXie Xiaobo } 19649f5befaSXie Xiaobo num++; 19749f5befaSXie Xiaobo #endif 19849f5befaSXie Xiaobo #ifdef CONFIG_TSEC3 19949f5befaSXie Xiaobo SET_STD_TSEC_INFO(tsec_info[num], 3); 20049f5befaSXie Xiaobo num++; 20149f5befaSXie Xiaobo #endif 20249f5befaSXie Xiaobo 20349f5befaSXie Xiaobo if (!num) { 20449f5befaSXie Xiaobo printf("No TSECs initialized\n"); 20549f5befaSXie Xiaobo return 0; 20649f5befaSXie Xiaobo } 20749f5befaSXie Xiaobo 20849f5befaSXie Xiaobo mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 20949f5befaSXie Xiaobo mdio_info.name = DEFAULT_MII_NAME; 21049f5befaSXie Xiaobo 21149f5befaSXie Xiaobo fsl_pq_mdio_init(bis, &mdio_info); 21249f5befaSXie Xiaobo 21349f5befaSXie Xiaobo tsec_eth_init(bis, tsec_info, num); 21449f5befaSXie Xiaobo 21549f5befaSXie Xiaobo #if defined(CONFIG_UEC_ETH) 21649f5befaSXie Xiaobo /* QE0 and QE3 need to be exposed for UCC1 21749f5befaSXie Xiaobo * and UCC5 Eth mode (in PMUXCR register). 21849f5befaSXie Xiaobo * Currently QE/LBC muxed pins assumed to be 21949f5befaSXie Xiaobo * LBC for U-Boot and PMUXCR updated by OS if required */ 22049f5befaSXie Xiaobo 22149f5befaSXie Xiaobo uec_standard_init(bis); 22249f5befaSXie Xiaobo #endif 22349f5befaSXie Xiaobo 22449f5befaSXie Xiaobo return pci_eth_init(bis); 22549f5befaSXie Xiaobo } 22649f5befaSXie Xiaobo 22749f5befaSXie Xiaobo #if defined(CONFIG_QE) 22849f5befaSXie Xiaobo static void fdt_board_fixup_qe_pins(void *blob) 22949f5befaSXie Xiaobo { 23049f5befaSXie Xiaobo int node; 23149f5befaSXie Xiaobo 23249f5befaSXie Xiaobo if (!hwconfig("qe")) { 23349f5befaSXie Xiaobo /* For QE and eLBC pins multiplexing, 23449f5befaSXie Xiaobo * When don't use QE function, remove 23549f5befaSXie Xiaobo * qe node from dt blob. 23649f5befaSXie Xiaobo */ 23749f5befaSXie Xiaobo node = fdt_path_offset(blob, "/qe"); 23849f5befaSXie Xiaobo if (node >= 0) 23949f5befaSXie Xiaobo fdt_del_node(blob, node); 24049f5befaSXie Xiaobo } else { 24149f5befaSXie Xiaobo /* For TWR Peripheral Modules - TWR-SER2 24249f5befaSXie Xiaobo * board only can support Signal Port MII, 24349f5befaSXie Xiaobo * so delete one UEC node when use MII port. 24449f5befaSXie Xiaobo */ 24549f5befaSXie Xiaobo if (hwconfig("mii")) 24649f5befaSXie Xiaobo node = fdt_path_offset(blob, "/qe/ucc@2400"); 24749f5befaSXie Xiaobo else 24849f5befaSXie Xiaobo node = fdt_path_offset(blob, "/qe/ucc@2000"); 24949f5befaSXie Xiaobo if (node >= 0) 25049f5befaSXie Xiaobo fdt_del_node(blob, node); 25149f5befaSXie Xiaobo } 25249f5befaSXie Xiaobo 25349f5befaSXie Xiaobo return; 25449f5befaSXie Xiaobo } 25549f5befaSXie Xiaobo #endif 25649f5befaSXie Xiaobo 25749f5befaSXie Xiaobo #ifdef CONFIG_OF_BOARD_SETUP 25849f5befaSXie Xiaobo void ft_board_setup(void *blob, bd_t *bd) 25949f5befaSXie Xiaobo { 26049f5befaSXie Xiaobo phys_addr_t base; 26149f5befaSXie Xiaobo phys_size_t size; 26249f5befaSXie Xiaobo 26349f5befaSXie Xiaobo ft_cpu_setup(blob, bd); 26449f5befaSXie Xiaobo 26549f5befaSXie Xiaobo base = getenv_bootm_low(); 26649f5befaSXie Xiaobo size = getenv_bootm_size(); 26749f5befaSXie Xiaobo 26849f5befaSXie Xiaobo fdt_fixup_memory(blob, (u64)base, (u64)size); 26949f5befaSXie Xiaobo 27049f5befaSXie Xiaobo FT_FSL_PCI_SETUP; 27149f5befaSXie Xiaobo 27249f5befaSXie Xiaobo #ifdef CONFIG_QE 27349f5befaSXie Xiaobo do_fixup_by_compat(blob, "fsl,qe", "status", "okay", 27449f5befaSXie Xiaobo sizeof("okay"), 0); 27549f5befaSXie Xiaobo #endif 27649f5befaSXie Xiaobo #if defined(CONFIG_TWR_P1025) 27749f5befaSXie Xiaobo fdt_board_fixup_qe_pins(blob); 27849f5befaSXie Xiaobo #endif 27949f5befaSXie Xiaobo fdt_fixup_dr_usb(blob, bd); 28049f5befaSXie Xiaobo } 28149f5befaSXie Xiaobo #endif 282