xref: /openbmc/u-boot/board/freescale/p1_twr/ddr.c (revision dd1033e4)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2013 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <asm/mmu.h>
8 #include <asm/immap_85xx.h>
9 #include <asm/processor.h>
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
12 #include <asm/io.h>
13 #include <asm/fsl_law.h>
14 
15 /* Fixed sdram init -- doesn't use serial presence detect. */
16 phys_size_t fixed_sdram(void)
17 {
18 	sys_info_t sysinfo;
19 	char buf[32];
20 	size_t ddr_size;
21 	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
22 		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
23 		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
24 		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
25 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
26 		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
27 		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
28 		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
29 #endif
30 		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
31 		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
32 		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
33 		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
34 		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
35 		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
36 		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
37 		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
38 		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
39 		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
40 		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
41 		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
42 		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
43 		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
44 		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
45 		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
46 		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
47 		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
48 		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
49 		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
50 		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
51 	};
52 
53 	get_sys_info(&sysinfo);
54 	printf("Configuring DDR for %s MT/s data rate\n",
55 			strmhz(buf, sysinfo.freq_ddrbus));
56 
57 	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
58 
59 	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
60 
61 	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
62 				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
63 		printf("ERROR setting Local Access Windows for DDR\n");
64 		return 0;
65 	};
66 
67 	return ddr_size;
68 }
69