1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 249f5befaSXie Xiaobo /* 349f5befaSXie Xiaobo * Copyright 2013 Freescale Semiconductor, Inc. 449f5befaSXie Xiaobo */ 549f5befaSXie Xiaobo 649f5befaSXie Xiaobo #include <common.h> 749f5befaSXie Xiaobo #include <asm/mmu.h> 849f5befaSXie Xiaobo #include <asm/immap_85xx.h> 949f5befaSXie Xiaobo #include <asm/processor.h> 105614e71bSYork Sun #include <fsl_ddr_sdram.h> 115614e71bSYork Sun #include <fsl_ddr_dimm_params.h> 1249f5befaSXie Xiaobo #include <asm/io.h> 1349f5befaSXie Xiaobo #include <asm/fsl_law.h> 1449f5befaSXie Xiaobo 1549f5befaSXie Xiaobo /* Fixed sdram init -- doesn't use serial presence detect. */ 1649f5befaSXie Xiaobo phys_size_t fixed_sdram(void) 1749f5befaSXie Xiaobo { 1849f5befaSXie Xiaobo sys_info_t sysinfo; 1949f5befaSXie Xiaobo char buf[32]; 2049f5befaSXie Xiaobo size_t ddr_size; 2149f5befaSXie Xiaobo fsl_ddr_cfg_regs_t ddr_cfg_regs = { 2249f5befaSXie Xiaobo .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, 2349f5befaSXie Xiaobo .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, 2449f5befaSXie Xiaobo .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, 2549f5befaSXie Xiaobo #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 2649f5befaSXie Xiaobo .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, 2749f5befaSXie Xiaobo .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, 2849f5befaSXie Xiaobo .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, 2949f5befaSXie Xiaobo #endif 3049f5befaSXie Xiaobo .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, 3149f5befaSXie Xiaobo .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, 3249f5befaSXie Xiaobo .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, 3349f5befaSXie Xiaobo .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, 3449f5befaSXie Xiaobo .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, 3549f5befaSXie Xiaobo .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 3649f5befaSXie Xiaobo .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, 3749f5befaSXie Xiaobo .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, 3849f5befaSXie Xiaobo .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, 3949f5befaSXie Xiaobo .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, 4049f5befaSXie Xiaobo .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, 4149f5befaSXie Xiaobo .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, 4249f5befaSXie Xiaobo .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, 4349f5befaSXie Xiaobo .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, 4449f5befaSXie Xiaobo .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, 4549f5befaSXie Xiaobo .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 4649f5befaSXie Xiaobo .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, 4749f5befaSXie Xiaobo .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, 4849f5befaSXie Xiaobo .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, 4949f5befaSXie Xiaobo .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, 5049f5befaSXie Xiaobo .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 5149f5befaSXie Xiaobo }; 5249f5befaSXie Xiaobo 5349f5befaSXie Xiaobo get_sys_info(&sysinfo); 5449f5befaSXie Xiaobo printf("Configuring DDR for %s MT/s data rate\n", 55997399faSPrabhakar Kushwaha strmhz(buf, sysinfo.freq_ddrbus)); 5649f5befaSXie Xiaobo 5749f5befaSXie Xiaobo ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 5849f5befaSXie Xiaobo 59c63e1370SYork Sun fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); 6049f5befaSXie Xiaobo 6149f5befaSXie Xiaobo if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, 6249f5befaSXie Xiaobo ddr_size, LAW_TRGT_IF_DDR_1) < 0) { 6349f5befaSXie Xiaobo printf("ERROR setting Local Access Windows for DDR\n"); 6449f5befaSXie Xiaobo return 0; 6549f5befaSXie Xiaobo }; 6649f5befaSXie Xiaobo 6749f5befaSXie Xiaobo return ddr_size; 6849f5befaSXie Xiaobo } 69