1*49f5befaSXie Xiaobo /* 2*49f5befaSXie Xiaobo * Copyright 2013 Freescale Semiconductor, Inc. 3*49f5befaSXie Xiaobo * 4*49f5befaSXie Xiaobo * This program is free software; you can redistribute it and/or 5*49f5befaSXie Xiaobo * modify it under the terms of the GNU General Public License 6*49f5befaSXie Xiaobo * Version 2 as published by the Free Software Foundation. 7*49f5befaSXie Xiaobo */ 8*49f5befaSXie Xiaobo 9*49f5befaSXie Xiaobo #include <common.h> 10*49f5befaSXie Xiaobo #include <asm/mmu.h> 11*49f5befaSXie Xiaobo #include <asm/immap_85xx.h> 12*49f5befaSXie Xiaobo #include <asm/processor.h> 13*49f5befaSXie Xiaobo #include <asm/fsl_ddr_sdram.h> 14*49f5befaSXie Xiaobo #include <asm/fsl_ddr_dimm_params.h> 15*49f5befaSXie Xiaobo #include <asm/io.h> 16*49f5befaSXie Xiaobo #include <asm/fsl_law.h> 17*49f5befaSXie Xiaobo 18*49f5befaSXie Xiaobo /* Fixed sdram init -- doesn't use serial presence detect. */ 19*49f5befaSXie Xiaobo phys_size_t fixed_sdram(void) 20*49f5befaSXie Xiaobo { 21*49f5befaSXie Xiaobo sys_info_t sysinfo; 22*49f5befaSXie Xiaobo char buf[32]; 23*49f5befaSXie Xiaobo size_t ddr_size; 24*49f5befaSXie Xiaobo fsl_ddr_cfg_regs_t ddr_cfg_regs = { 25*49f5befaSXie Xiaobo .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, 26*49f5befaSXie Xiaobo .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, 27*49f5befaSXie Xiaobo .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, 28*49f5befaSXie Xiaobo #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 29*49f5befaSXie Xiaobo .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, 30*49f5befaSXie Xiaobo .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, 31*49f5befaSXie Xiaobo .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, 32*49f5befaSXie Xiaobo #endif 33*49f5befaSXie Xiaobo .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, 34*49f5befaSXie Xiaobo .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, 35*49f5befaSXie Xiaobo .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, 36*49f5befaSXie Xiaobo .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, 37*49f5befaSXie Xiaobo .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, 38*49f5befaSXie Xiaobo .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 39*49f5befaSXie Xiaobo .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, 40*49f5befaSXie Xiaobo .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, 41*49f5befaSXie Xiaobo .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, 42*49f5befaSXie Xiaobo .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, 43*49f5befaSXie Xiaobo .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, 44*49f5befaSXie Xiaobo .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, 45*49f5befaSXie Xiaobo .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, 46*49f5befaSXie Xiaobo .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, 47*49f5befaSXie Xiaobo .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, 48*49f5befaSXie Xiaobo .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 49*49f5befaSXie Xiaobo .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, 50*49f5befaSXie Xiaobo .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, 51*49f5befaSXie Xiaobo .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, 52*49f5befaSXie Xiaobo .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, 53*49f5befaSXie Xiaobo .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 54*49f5befaSXie Xiaobo }; 55*49f5befaSXie Xiaobo 56*49f5befaSXie Xiaobo get_sys_info(&sysinfo); 57*49f5befaSXie Xiaobo printf("Configuring DDR for %s MT/s data rate\n", 58*49f5befaSXie Xiaobo strmhz(buf, sysinfo.freqDDRBus)); 59*49f5befaSXie Xiaobo 60*49f5befaSXie Xiaobo ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 61*49f5befaSXie Xiaobo 62*49f5befaSXie Xiaobo fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); 63*49f5befaSXie Xiaobo 64*49f5befaSXie Xiaobo if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, 65*49f5befaSXie Xiaobo ddr_size, LAW_TRGT_IF_DDR_1) < 0) { 66*49f5befaSXie Xiaobo printf("ERROR setting Local Access Windows for DDR\n"); 67*49f5befaSXie Xiaobo return 0; 68*49f5befaSXie Xiaobo }; 69*49f5befaSXie Xiaobo 70*49f5befaSXie Xiaobo return ddr_size; 71*49f5befaSXie Xiaobo } 72