1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/mmu.h> 25 26 struct fsl_e_tlb_entry tlb_table[] = { 27 /* TLB 0 - for temp stack in cache */ 28 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 29 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 30 MAS3_SX|MAS3_SW|MAS3_SR, 0, 31 0, 0, BOOKE_PAGESZ_4K, 0), 32 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 33 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 34 MAS3_SX|MAS3_SW|MAS3_SR, 0, 35 0, 0, BOOKE_PAGESZ_4K, 0), 36 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 37 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 38 MAS3_SX|MAS3_SW|MAS3_SR, 0, 39 0, 0, BOOKE_PAGESZ_4K, 0), 40 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 41 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 42 MAS3_SX|MAS3_SW|MAS3_SR, 0, 43 0, 0, BOOKE_PAGESZ_4K, 0), 44 45 /* TLB 1 */ 46 /* *I*** - Covers boot page */ 47 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 48 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 49 0, 0, BOOKE_PAGESZ_4K, 1), 50 51 /* *I*G* - CCSRBAR */ 52 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 53 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54 0, 1, BOOKE_PAGESZ_1M, 1), 55 56 #ifndef CONFIG_SPL_BUILD 57 /* W**G* - Flash/promjet, localbus */ 58 /* This will be changed to *I*G* after relocation to RAM. */ 59 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 60 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 61 0, 2, BOOKE_PAGESZ_64M, 1), 62 63 #ifdef CONFIG_PCI 64 /* *I*G* - PCI memory 1.5G */ 65 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67 0, 3, BOOKE_PAGESZ_1G, 1), 68 69 /* *I*G* - PCI I/O effective: 192K */ 70 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 71 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 72 0, 4, BOOKE_PAGESZ_256K, 1), 73 #endif 74 75 #ifdef CONFIG_VSC7385_ENET 76 /* *I*G - VSC7385 Switch */ 77 SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, 78 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 79 0, 5, BOOKE_PAGESZ_1M, 1), 80 #endif 81 82 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 83 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84 0, 6, BOOKE_PAGESZ_1M, 1), 85 SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS, 86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 87 0, 10, BOOKE_PAGESZ_64K, 1), 88 #endif /* not SPL */ 89 90 #ifdef CONFIG_SYS_NAND_BASE 91 /* *I*G - NAND */ 92 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 93 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 94 0, 7, BOOKE_PAGESZ_1M, 1), 95 #endif 96 97 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 98 #ifdef CONFIG_SYS_INIT_L2_ADDR 99 /* L2SRAM */ 100 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 101 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 102 0, 8, BOOKE_PAGESZ_256K, 1), 103 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, 104 CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, 105 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 106 0, 12, BOOKE_PAGESZ_256K, 1), 107 #else 108 /* *I*G - eSDHC/eSPI/NAND boot */ 109 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 110 MAS3_SX|MAS3_SW|MAS3_SR, 0, 111 0, 8, BOOKE_PAGESZ_1G, 1), 112 113 #ifdef CONFIG_P1020MBG 114 /* 2G DDR on P1020MBG, map the second 1G */ 115 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 116 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 117 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 118 0, 9, BOOKE_PAGESZ_1G, 1), 119 #endif /* P1020MBG */ 120 #endif /* not L2 SRAM */ 121 #endif /* RAMBOOT/SPL */ 122 }; 123 124 int num_tlb_entries = ARRAY_SIZE(tlb_table); 125