1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/mmu.h> 9 10 struct fsl_e_tlb_entry tlb_table[] = { 11 /* TLB 0 - for temp stack in cache */ 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14 MAS3_SX|MAS3_SW|MAS3_SR, 0, 15 0, 0, BOOKE_PAGESZ_4K, 0), 16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 17 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18 MAS3_SX|MAS3_SW|MAS3_SR, 0, 19 0, 0, BOOKE_PAGESZ_4K, 0), 20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 21 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22 MAS3_SX|MAS3_SW|MAS3_SR, 0, 23 0, 0, BOOKE_PAGESZ_4K, 0), 24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 25 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26 MAS3_SX|MAS3_SW|MAS3_SR, 0, 27 0, 0, BOOKE_PAGESZ_4K, 0), 28 29 /* TLB 1 */ 30 /* *I*** - Covers boot page */ 31 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 32 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 33 0, 0, BOOKE_PAGESZ_4K, 1), 34 35 /* *I*G* - CCSRBAR */ 36 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 37 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 38 0, 1, BOOKE_PAGESZ_1M, 1), 39 40 #ifndef CONFIG_SPL_BUILD 41 /* W**G* - Flash/promjet, localbus */ 42 /* This will be changed to *I*G* after relocation to RAM. */ 43 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 44 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 45 0, 2, BOOKE_PAGESZ_64M, 1), 46 47 #ifdef CONFIG_PCI 48 /* *I*G* - PCI memory 1.5G */ 49 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51 0, 3, BOOKE_PAGESZ_1G, 1), 52 53 /* *I*G* - PCI I/O effective: 192K */ 54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 55 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 56 0, 4, BOOKE_PAGESZ_256K, 1), 57 #endif 58 59 #ifdef CONFIG_VSC7385_ENET 60 /* *I*G - VSC7385 Switch */ 61 SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, 62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63 0, 5, BOOKE_PAGESZ_1M, 1), 64 #endif 65 66 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 68 0, 6, BOOKE_PAGESZ_1M, 1), 69 SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS, 70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 71 0, 10, BOOKE_PAGESZ_64K, 1), 72 #endif /* not SPL */ 73 74 #ifdef CONFIG_SYS_NAND_BASE 75 /* *I*G - NAND */ 76 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 77 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 78 0, 7, BOOKE_PAGESZ_1M, 1), 79 #endif 80 81 #if defined(CONFIG_SYS_RAMBOOT) || \ 82 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) 83 /* *I*G - eSDHC/eSPI/NAND boot */ 84 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 85 MAS3_SX|MAS3_SW|MAS3_SR, 0, 86 0, 8, BOOKE_PAGESZ_1G, 1), 87 88 #if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD) 89 /* 2G DDR on P1020MBG, map the second 1G */ 90 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 91 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 92 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 93 0, 9, BOOKE_PAGESZ_1G, 1), 94 #endif /* TARGET_P1020MBG */ 95 #endif /* RAMBOOT/SPL */ 96 97 #ifdef CONFIG_SYS_INIT_L2_ADDR 98 /* *I*G - L2SRAM */ 99 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 100 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 101 0, 11, BOOKE_PAGESZ_256K, 1), 102 #if CONFIG_SYS_L2_SIZE >= (256 << 10) 103 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, 104 CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, 105 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 106 0, 12, BOOKE_PAGESZ_256K, 1) 107 #endif 108 #endif 109 }; 110 111 int num_tlb_entries = ARRAY_SIZE(tlb_table); 112