1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <ns16550.h> 9 #include <asm/io.h> 10 #include <nand.h> 11 #include <linux/compiler.h> 12 #include <asm/fsl_law.h> 13 #include <asm/fsl_ddr_sdram.h> 14 #include <asm/global_data.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 #ifndef CONFIG_SYS_INIT_L2_ADDR 19 /* 20 * Fixed sdram init -- doesn't use serial presence detect. 21 */ 22 static void sdram_init(void) 23 { 24 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; 25 26 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); 27 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); 28 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 29 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); 30 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); 31 #endif 32 __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); 33 __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); 34 __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); 35 __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); 36 37 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); 38 __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); 39 __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); 40 41 __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); 42 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); 43 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); 44 45 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); 46 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); 47 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); 48 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); 49 50 /* Set, but do not enable the memory */ 51 __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); 52 53 asm volatile("sync;isync"); 54 udelay(500); 55 56 /* Let the controller go */ 57 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); 58 59 set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); 60 } 61 #endif 62 63 void board_init_f(ulong bootflag) 64 { 65 u32 plat_ratio; 66 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 67 #ifndef CONFIG_QE 68 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 69 #elif defined(CONFIG_P1021RDB) 70 par_io_t *par_io = (par_io_t *)&(gur->qe_par_io); 71 #endif 72 73 /* initialize selected port with appropriate baud rate */ 74 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 75 plat_ratio >>= 1; 76 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; 77 78 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 79 gd->bus_clk / 16 / CONFIG_BAUDRATE); 80 81 puts("\nNAND boot... "); 82 83 #ifndef CONFIG_QE 84 /* init DDR3 reset signal */ 85 __raw_writel(0x02000000, &pgpio->gpdir); 86 __raw_writel(0x00200000, &pgpio->gpodr); 87 __raw_writel(0x00000000, &pgpio->gpdat); 88 udelay(1000); 89 __raw_writel(0x00200000, &pgpio->gpdat); 90 udelay(1000); 91 __raw_writel(0x00000000, &pgpio->gpdir); 92 #elif defined(CONFIG_P1021RDB) 93 /* init DDR3 reset signal CE_PB8 */ 94 out_be32(&par_io[1].cpdir1, 0x00004000); 95 out_be32(&par_io[1].cpodr, 0x00800000); 96 out_be32(&par_io[1].cppar1, 0x00000000); 97 /* reset DDR3 */ 98 out_be32(&par_io[1].cpdat, 0x00800000); 99 udelay(1000); 100 out_be32(&par_io[1].cpdat, 0x00000000); 101 udelay(1000); 102 out_be32(&par_io[1].cpdat, 0x00800000); 103 /* disable the CE_PB8 */ 104 out_be32(&par_io[1].cpdir1, 0x00000000); 105 #endif 106 107 #ifndef CONFIG_SYS_INIT_L2_ADDR 108 /* Initialize the DDR3 */ 109 sdram_init(); 110 #endif 111 112 /* copy code to RAM and jump to it - this should not return */ 113 /* NOTE - code has to be copied out of NAND buffer before 114 * other blocks can be read. 115 */ 116 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); 117 } 118 119 void board_init_r(gd_t *gd, ulong dest_addr) 120 { 121 nand_boot(); 122 } 123 124 void putc(char c) 125 { 126 if (c == '\n') 127 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); 128 129 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); 130 } 131 132 void puts(const char *str) 133 { 134 while (*str) 135 putc(*str++); 136 } 137