1 /* 2 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <hwconfig.h> 10 #include <pci.h> 11 #include <i2c.h> 12 #include <asm/processor.h> 13 #include <asm/mmu.h> 14 #include <asm/cache.h> 15 #include <asm/immap_85xx.h> 16 #include <asm/fsl_pci.h> 17 #include <fsl_ddr_sdram.h> 18 #include <asm/io.h> 19 #include <asm/fsl_law.h> 20 #include <asm/fsl_lbc.h> 21 #include <asm/mp.h> 22 #include <miiphy.h> 23 #include <libfdt.h> 24 #include <fdt_support.h> 25 #include <fsl_mdio.h> 26 #include <tsec.h> 27 #include <vsc7385.h> 28 #include <ioports.h> 29 #include <asm/fsl_serdes.h> 30 #include <netdev.h> 31 32 #ifdef CONFIG_QE 33 34 #define GPIO_GETH_SW_PORT 1 35 #define GPIO_GETH_SW_PIN 29 36 #define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN)) 37 38 #define GPIO_SLIC_PORT 1 39 #define GPIO_SLIC_PIN 30 40 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN)) 41 42 #if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) 43 #define GPIO_DDR_RST_PORT 1 44 #define GPIO_DDR_RST_PIN 8 45 #define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN)) 46 47 #define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2)) 48 #endif 49 50 #if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB) 51 #define PCA_IOPORT_I2C_ADDR 0x23 52 #define PCA_IOPORT_OUTPUT_CMD 0x2 53 #define PCA_IOPORT_CFG_CMD 0x6 54 #define PCA_IOPORT_QE_PIN_ENABLE 0xf8 55 #define PCA_IOPORT_QE_TDM_ENABLE 0xf6 56 #endif 57 58 const qe_iop_conf_t qe_iop_conf_tab[] = { 59 /* GPIO */ 60 {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */ 61 #if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) 62 {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */ 63 #endif 64 {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ 65 {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */ 66 {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */ 67 68 #ifdef CONFIG_P1025RDB 69 /* QE_MUX_MDC */ 70 {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ 71 72 /* QE_MUX_MDIO */ 73 {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ 74 75 /* UCC_1_MII */ 76 {0, 23, 2, 0, 2}, /* CLK12 */ 77 {0, 24, 2, 0, 1}, /* CLK9 */ 78 {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ 79 {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ 80 {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ 81 {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ 82 {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ 83 {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ 84 {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ 85 {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ 86 {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 87 {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ 88 {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ 89 {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ 90 {0, 17, 2, 0, 2}, /* ENET1_CRS */ 91 {0, 16, 2, 0, 2}, /* ENET1_COL */ 92 93 /* UCC_5_RMII */ 94 {1, 11, 2, 0, 1}, /* CLK13 */ 95 {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ 96 {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ 97 {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ 98 {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ 99 {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ 100 {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ 101 {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ 102 #endif 103 104 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 105 }; 106 #endif 107 108 struct cpld_data { 109 u8 cpld_rev_major; 110 u8 pcba_rev; 111 u8 wd_cfg; 112 u8 rst_bps_sw; 113 u8 load_default_n; 114 u8 rst_bps_wd; 115 u8 bypass_enable; 116 u8 bps_led; 117 u8 status_led; /* offset: 0x8 */ 118 u8 fxo_led; /* offset: 0x9 */ 119 u8 fxs_led; /* offset: 0xa */ 120 u8 rev4[2]; 121 u8 system_rst; /* offset: 0xd */ 122 u8 bps_out; 123 u8 rev5[3]; 124 u8 cpld_rev_minor; 125 }; 126 127 #define CPLD_WD_CFG 0x03 128 #define CPLD_RST_BSW 0x00 129 #define CPLD_RST_BWD 0x00 130 #define CPLD_BYPASS_EN 0x03 131 #define CPLD_STATUS_LED 0x01 132 #define CPLD_FXO_LED 0x01 133 #define CPLD_FXS_LED 0x0F 134 #define CPLD_SYS_RST 0x00 135 136 void board_cpld_init(void) 137 { 138 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 139 140 out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); 141 out_8(&cpld_data->status_led, CPLD_STATUS_LED); 142 out_8(&cpld_data->fxo_led, CPLD_FXO_LED); 143 out_8(&cpld_data->fxs_led, CPLD_FXS_LED); 144 out_8(&cpld_data->system_rst, CPLD_SYS_RST); 145 } 146 147 void board_gpio_init(void) 148 { 149 #ifdef CONFIG_QE 150 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 151 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); 152 153 #if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) 154 /* reset DDR3 */ 155 setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); 156 udelay(1000); 157 clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); 158 udelay(1000); 159 setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); 160 /* disable CE_PB8 */ 161 clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK); 162 #endif 163 /* Enable VSC7385 switch */ 164 setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA); 165 166 /* Enable SLIC */ 167 setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA); 168 #else 169 170 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 171 172 /* 173 * GPIO10 DDR Reset, open drain 174 * GPIO7 LOAD_DEFAULT_N Input 175 * GPIO11 WDI (watchdog input) 176 * GPIO12 Ethernet Switch Reset 177 * GPIO13 SLIC Reset 178 */ 179 180 setbits_be32(&pgpio->gpdir, 0x02130000); 181 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) 182 /* init DDR3 reset signal */ 183 setbits_be32(&pgpio->gpdir, 0x00200000); 184 setbits_be32(&pgpio->gpodr, 0x00200000); 185 clrbits_be32(&pgpio->gpdat, 0x00200000); 186 udelay(1000); 187 setbits_be32(&pgpio->gpdat, 0x00200000); 188 udelay(1000); 189 clrbits_be32(&pgpio->gpdir, 0x00200000); 190 #endif 191 192 #ifdef CONFIG_VSC7385_ENET 193 /* reset VSC7385 Switch */ 194 setbits_be32(&pgpio->gpdir, 0x00080000); 195 setbits_be32(&pgpio->gpdat, 0x00080000); 196 #endif 197 198 #ifdef CONFIG_SLIC 199 /* reset SLIC */ 200 setbits_be32(&pgpio->gpdir, 0x00040000); 201 setbits_be32(&pgpio->gpdat, 0x00040000); 202 #endif 203 #endif 204 } 205 206 int board_early_init_f(void) 207 { 208 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 209 210 setbits_be32(&gur->pmuxcr, 211 (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); 212 clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); 213 214 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); 215 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA); 216 217 board_gpio_init(); 218 board_cpld_init(); 219 220 return 0; 221 } 222 223 int checkboard(void) 224 { 225 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 226 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 227 u8 in, out, io_config, val; 228 229 printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME, 230 in_8(&cpld_data->cpld_rev_major) & 0x0F, 231 in_8(&cpld_data->cpld_rev_minor) & 0x0F, 232 in_8(&cpld_data->pcba_rev) & 0x0F); 233 234 /* Initialize i2c early for rom_loc and flash bank information */ 235 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); 236 237 if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || 238 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || 239 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { 240 printf("Error reading i2c boot information!\n"); 241 return 0; /* Don't want to hang() on this error */ 242 } 243 244 val = (in & io_config) | (out & (~io_config)); 245 246 puts("rom_loc: "); 247 if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { 248 puts("sd"); 249 #ifdef __SW_BOOT_SPI 250 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) { 251 puts("spi"); 252 #endif 253 #ifdef __SW_BOOT_NAND 254 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) { 255 puts("nand"); 256 #endif 257 #ifdef __SW_BOOT_PCIE 258 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) { 259 puts("pcie"); 260 #endif 261 } else { 262 if (val & 0x2) 263 puts("nor lower bank"); 264 else 265 puts("nor upper bank"); 266 } 267 puts("\n"); 268 269 if (val & 0x1) { 270 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); 271 puts("SD/MMC : 8-bit Mode\n"); 272 puts("eSPI : Disabled\n"); 273 } else { 274 puts("SD/MMC : 4-bit Mode\n"); 275 puts("eSPI : Enabled\n"); 276 } 277 278 return 0; 279 } 280 281 #ifdef CONFIG_PCI 282 void pci_init_board(void) 283 { 284 fsl_pcie_init_board(0); 285 } 286 #endif 287 288 int board_early_init_r(void) 289 { 290 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 291 int flash_esel = find_tlb_idx((void *)flashbase, 1); 292 293 /* 294 * Remap Boot flash region to caching-inhibited 295 * so that flash can be erased properly. 296 */ 297 298 /* Flush d-cache and invalidate i-cache of any FLASH data */ 299 flush_dcache(); 300 invalidate_icache(); 301 302 if (flash_esel == -1) { 303 /* very unlikely unless something is messed up */ 304 puts("Error: Could not find TLB for FLASH BASE\n"); 305 flash_esel = 2; /* give our best effort to continue */ 306 } else { 307 /* invalidate existing TLB entry for flash */ 308 disable_tlb(flash_esel); 309 } 310 311 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 312 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ 313 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ 314 return 0; 315 } 316 317 int board_eth_init(bd_t *bis) 318 { 319 struct fsl_pq_mdio_info mdio_info; 320 struct tsec_info_struct tsec_info[4]; 321 ccsr_gur_t *gur __attribute__((unused)) = 322 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 323 int num = 0; 324 #ifdef CONFIG_VSC7385_ENET 325 char *tmp; 326 unsigned int vscfw_addr; 327 #endif 328 329 #ifdef CONFIG_TSEC1 330 SET_STD_TSEC_INFO(tsec_info[num], 1); 331 num++; 332 #endif 333 #ifdef CONFIG_TSEC2 334 SET_STD_TSEC_INFO(tsec_info[num], 2); 335 if (is_serdes_configured(SGMII_TSEC2)) { 336 printf("eTSEC2 is in sgmii mode.\n"); 337 tsec_info[num].flags |= TSEC_SGMII; 338 } 339 num++; 340 #endif 341 #ifdef CONFIG_TSEC3 342 SET_STD_TSEC_INFO(tsec_info[num], 3); 343 num++; 344 #endif 345 346 if (!num) { 347 printf("No TSECs initialized\n"); 348 return 0; 349 } 350 351 #ifdef CONFIG_VSC7385_ENET 352 /* If a VSC7385 microcode image is present, then upload it. */ 353 if ((tmp = getenv("vscfw_addr")) != NULL) { 354 vscfw_addr = simple_strtoul(tmp, NULL, 16); 355 printf("uploading VSC7385 microcode from %x\n", vscfw_addr); 356 if (vsc7385_upload_firmware((void *) vscfw_addr, 357 CONFIG_VSC7385_IMAGE_SIZE)) 358 puts("Failure uploading VSC7385 microcode.\n"); 359 } else 360 puts("No address specified for VSC7385 microcode.\n"); 361 #endif 362 363 mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); 364 mdio_info.name = DEFAULT_MII_NAME; 365 366 fsl_pq_mdio_init(bis, &mdio_info); 367 368 tsec_eth_init(bis, tsec_info, num); 369 370 #if defined(CONFIG_UEC_ETH) 371 /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */ 372 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0); 373 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3); 374 375 uec_standard_init(bis); 376 #endif 377 378 return pci_eth_init(bis); 379 } 380 381 #if defined(CONFIG_QE) && \ 382 (defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)) 383 static void fdt_board_fixup_qe_pins(void *blob) 384 { 385 unsigned int oldbus; 386 u8 val8; 387 int node; 388 fsl_lbc_t *lbc = LBC_BASE_ADDR; 389 390 if (hwconfig("qe")) { 391 /* For QE and eLBC pins multiplexing, 392 * there is a PCA9555 device on P1025RDB. 393 * It control the multiplex pins' functions, 394 * and setting the PCA9555 can switch the 395 * function between QE and eLBC. 396 */ 397 oldbus = i2c_get_bus_num(); 398 i2c_set_bus_num(0); 399 if (hwconfig("tdm")) 400 val8 = PCA_IOPORT_QE_TDM_ENABLE; 401 else 402 val8 = PCA_IOPORT_QE_PIN_ENABLE; 403 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD, 404 1, &val8, 1); 405 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD, 406 1, &val8, 1); 407 i2c_set_bus_num(oldbus); 408 /* if run QE TDM, Set ABSWP to implement 409 * conversion of addresses in the eLBC. 410 */ 411 if (hwconfig("tdm")) { 412 set_lbc_or(2, CONFIG_PMC_OR_PRELIM); 413 set_lbc_br(2, CONFIG_PMC_BR_PRELIM); 414 setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); 415 } 416 } else { 417 node = fdt_path_offset(blob, "/qe"); 418 if (node >= 0) 419 fdt_del_node(blob, node); 420 } 421 422 return; 423 } 424 #endif 425 426 #ifdef CONFIG_OF_BOARD_SETUP 427 int ft_board_setup(void *blob, bd_t *bd) 428 { 429 phys_addr_t base; 430 phys_size_t size; 431 #if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC) 432 const char *soc_usb_compat = "fsl-usb2-dr"; 433 int usb_err, usb1_off, usb2_off; 434 #endif 435 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 436 int err; 437 #endif 438 439 ft_cpu_setup(blob, bd); 440 441 base = getenv_bootm_low(); 442 size = getenv_bootm_size(); 443 444 fdt_fixup_memory(blob, (u64)base, (u64)size); 445 446 FT_FSL_PCI_SETUP; 447 448 #ifdef CONFIG_QE 449 do_fixup_by_compat(blob, "fsl,qe", "status", "okay", 450 sizeof("okay"), 0); 451 #if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB) 452 fdt_board_fixup_qe_pins(blob); 453 #endif 454 #endif 455 456 #if defined(CONFIG_HAS_FSL_DR_USB) 457 fsl_fdt_fixup_dr_usb(blob, bd); 458 #endif 459 460 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 461 /* Delete eLBC node as it is muxed with USB2 controller */ 462 if (hwconfig("usb2")) { 463 const char *soc_elbc_compat = "fsl,p1020-elbc"; 464 int off = fdt_node_offset_by_compatible(blob, -1, 465 soc_elbc_compat); 466 if (off < 0) { 467 printf("WARNING: could not find compatible node %s\n", 468 soc_elbc_compat); 469 return off; 470 } 471 err = fdt_del_node(blob, off); 472 if (err < 0) { 473 printf("WARNING: could not remove %s\n", 474 soc_elbc_compat); 475 return err; 476 } 477 return 0; 478 } 479 #endif 480 481 #if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC) 482 /* Delete USB2 node as it is muxed with eLBC */ 483 usb1_off = fdt_node_offset_by_compatible(blob, -1, 484 soc_usb_compat); 485 if (usb1_off < 0) { 486 printf("WARNING: could not find compatible node %s\n", 487 soc_usb_compat); 488 return usb1_off; 489 } 490 usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, 491 soc_usb_compat); 492 if (usb2_off < 0) { 493 printf("WARNING: could not find compatible node %s\n", 494 soc_usb_compat); 495 return usb2_off; 496 } 497 usb_err = fdt_del_node(blob, usb2_off); 498 if (usb_err < 0) { 499 printf("WARNING: could not remove %s\n", soc_usb_compat); 500 return usb_err; 501 } 502 #endif 503 504 return 0; 505 } 506 #endif 507