1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/mmu.h> 8 #include <asm/immap_85xx.h> 9 #include <asm/processor.h> 10 #include <fsl_ddr_sdram.h> 11 #include <fsl_ddr_dimm_params.h> 12 #include <asm/io.h> 13 #include <asm/fsl_law.h> 14 15 #ifdef CONFIG_SYS_DDR_RAW_TIMING 16 #if defined(CONFIG_P1020RDB_PROTO) || \ 17 defined(CONFIG_TARGET_P1021RDB) || \ 18 defined(CONFIG_TARGET_P1020UTM) 19 /* Micron MT41J256M8_187E */ 20 dimm_params_t ddr_raw_timing = { 21 .n_ranks = 1, 22 .rank_density = 1073741824u, 23 .capacity = 1073741824u, 24 .primary_sdram_width = 32, 25 .ec_sdram_width = 0, 26 .registered_dimm = 0, 27 .mirrored_dimm = 0, 28 .n_row_addr = 15, 29 .n_col_addr = 10, 30 .n_banks_per_sdram_device = 8, 31 .edc_config = 0, 32 .burst_lengths_bitmask = 0x0c, 33 34 .tckmin_x_ps = 1870, 35 .caslat_x = 0x1e << 4, /* 5,6,7,8 */ 36 .taa_ps = 13125, 37 .twr_ps = 15000, 38 .trcd_ps = 13125, 39 .trrd_ps = 7500, 40 .trp_ps = 13125, 41 .tras_ps = 37500, 42 .trc_ps = 50625, 43 .trfc_ps = 160000, 44 .twtr_ps = 7500, 45 .trtp_ps = 7500, 46 .refresh_rate_ps = 7800000, 47 .tfaw_ps = 37500, 48 }; 49 #elif defined(CONFIG_TARGET_P2020RDB) 50 /* Micron MT41J128M16_15E */ 51 dimm_params_t ddr_raw_timing = { 52 .n_ranks = 1, 53 .rank_density = 1073741824u, 54 .capacity = 1073741824u, 55 .primary_sdram_width = 64, 56 .ec_sdram_width = 0, 57 .registered_dimm = 0, 58 .mirrored_dimm = 0, 59 .n_row_addr = 14, 60 .n_col_addr = 10, 61 .n_banks_per_sdram_device = 8, 62 .edc_config = 0, 63 .burst_lengths_bitmask = 0x0c, 64 65 .tckmin_x_ps = 1500, 66 .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ 67 .taa_ps = 13500, 68 .twr_ps = 15000, 69 .trcd_ps = 13500, 70 .trrd_ps = 6000, 71 .trp_ps = 13500, 72 .tras_ps = 36000, 73 .trc_ps = 49500, 74 .trfc_ps = 160000, 75 .twtr_ps = 7500, 76 .trtp_ps = 7500, 77 .refresh_rate_ps = 7800000, 78 .tfaw_ps = 30000, 79 }; 80 #elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 81 /* Micron MT41J512M8_187E */ 82 dimm_params_t ddr_raw_timing = { 83 .n_ranks = 2, 84 .rank_density = 1073741824u, 85 .capacity = 2147483648u, 86 .primary_sdram_width = 32, 87 .ec_sdram_width = 0, 88 .registered_dimm = 0, 89 .mirrored_dimm = 0, 90 .n_row_addr = 15, 91 .n_col_addr = 10, 92 .n_banks_per_sdram_device = 8, 93 .edc_config = 0, 94 .burst_lengths_bitmask = 0x0c, 95 96 .tckmin_x_ps = 1870, 97 .caslat_x = 0x1e << 4, /* 5,6,7,8 */ 98 .taa_ps = 13125, 99 .twr_ps = 15000, 100 .trcd_ps = 13125, 101 .trrd_ps = 7500, 102 .trp_ps = 13125, 103 .tras_ps = 37500, 104 .trc_ps = 50625, 105 .trfc_ps = 160000, 106 .twtr_ps = 7500, 107 .trtp_ps = 7500, 108 .refresh_rate_ps = 7800000, 109 .tfaw_ps = 37500, 110 }; 111 #elif defined(CONFIG_TARGET_P1020RDB_PC) 112 /* 113 * Samsung K4B2G0846C-HCF8 114 * The following timing are for "downshift" 115 * i.e. to use CL9 part as CL7 116 * otherwise, tAA, tRCD, tRP will be 13500ps 117 * and tRC will be 49500ps 118 */ 119 dimm_params_t ddr_raw_timing = { 120 .n_ranks = 1, 121 .rank_density = 1073741824u, 122 .capacity = 1073741824u, 123 .primary_sdram_width = 32, 124 .ec_sdram_width = 0, 125 .registered_dimm = 0, 126 .mirrored_dimm = 0, 127 .n_row_addr = 15, 128 .n_col_addr = 10, 129 .n_banks_per_sdram_device = 8, 130 .edc_config = 0, 131 .burst_lengths_bitmask = 0x0c, 132 133 .tckmin_x_ps = 1875, 134 .caslat_x = 0x1e << 4, /* 5,6,7,8 */ 135 .taa_ps = 13125, 136 .twr_ps = 15000, 137 .trcd_ps = 13125, 138 .trrd_ps = 7500, 139 .trp_ps = 13125, 140 .tras_ps = 37500, 141 .trc_ps = 50625, 142 .trfc_ps = 160000, 143 .twtr_ps = 7500, 144 .trtp_ps = 7500, 145 .refresh_rate_ps = 7800000, 146 .tfaw_ps = 37500, 147 }; 148 #elif defined(CONFIG_TARGET_P1024RDB) || \ 149 defined(CONFIG_TARGET_P1025RDB) 150 /* 151 * Samsung K4B2G0846C-HCH9 152 * The following timing are for "downshift" 153 * i.e. to use CL9 part as CL7 154 * otherwise, tAA, tRCD, tRP will be 13500ps 155 * and tRC will be 49500ps 156 */ 157 dimm_params_t ddr_raw_timing = { 158 .n_ranks = 1, 159 .rank_density = 1073741824u, 160 .capacity = 1073741824u, 161 .primary_sdram_width = 32, 162 .ec_sdram_width = 0, 163 .registered_dimm = 0, 164 .mirrored_dimm = 0, 165 .n_row_addr = 15, 166 .n_col_addr = 10, 167 .n_banks_per_sdram_device = 8, 168 .edc_config = 0, 169 .burst_lengths_bitmask = 0x0c, 170 171 .tckmin_x_ps = 1500, 172 .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */ 173 .taa_ps = 13125, 174 .twr_ps = 15000, 175 .trcd_ps = 13125, 176 .trrd_ps = 6000, 177 .trp_ps = 13125, 178 .tras_ps = 36000, 179 .trc_ps = 49125, 180 .trfc_ps = 160000, 181 .twtr_ps = 7500, 182 .trtp_ps = 7500, 183 .refresh_rate_ps = 7800000, 184 .tfaw_ps = 30000, 185 }; 186 #else 187 #error Missing raw timing data for this board 188 #endif 189 190 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 191 unsigned int controller_number, 192 unsigned int dimm_number) 193 { 194 const char dimm_model[] = "Fixed DDR on board"; 195 196 if ((controller_number == 0) && (dimm_number == 0)) { 197 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 198 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 199 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 200 } 201 202 return 0; 203 } 204 #endif /* CONFIG_SYS_DDR_RAW_TIMING */ 205 206 #ifdef CONFIG_SYS_DDR_CS0_BNDS 207 /* Fixed sdram init -- doesn't use serial presence detect. */ 208 phys_size_t fixed_sdram(void) 209 { 210 sys_info_t sysinfo; 211 char buf[32]; 212 size_t ddr_size; 213 fsl_ddr_cfg_regs_t ddr_cfg_regs = { 214 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, 215 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, 216 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, 217 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 218 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, 219 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, 220 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, 221 #endif 222 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, 223 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, 224 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, 225 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, 226 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, 227 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 228 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, 229 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, 230 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, 231 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, 232 .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, 233 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, 234 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, 235 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, 236 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, 237 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 238 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, 239 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, 240 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, 241 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, 242 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 243 }; 244 245 get_sys_info(&sysinfo); 246 printf("Configuring DDR for %s MT/s data rate\n", 247 strmhz(buf, sysinfo.freq_ddrbus)); 248 249 ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 250 251 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); 252 253 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, 254 ddr_size, LAW_TRGT_IF_DDR_1) < 0) { 255 printf("ERROR setting Local Access Windows for DDR\n"); 256 return 0; 257 }; 258 259 return ddr_size; 260 } 261 #endif 262 263 void fsl_ddr_board_options(memctl_options_t *popts, 264 dimm_params_t *pdimm, 265 unsigned int ctrl_num) 266 { 267 int i; 268 popts->clk_adjust = 6; 269 popts->cpo_override = 0x1f; 270 popts->write_data_delay = 2; 271 popts->half_strength_driver_enable = 1; 272 /* Write leveling override */ 273 popts->wrlvl_en = 1; 274 popts->wrlvl_override = 1; 275 popts->wrlvl_sample = 0xf; 276 popts->wrlvl_start = 0x8; 277 popts->trwt_override = 1; 278 popts->trwt = 0; 279 280 if (pdimm->primary_sdram_width == 64) 281 popts->data_bus_width = 0; 282 else if (pdimm->primary_sdram_width == 32) 283 popts->data_bus_width = 1; 284 else 285 printf("Error in DDR bus width configuration!\n"); 286 287 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 288 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 289 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 290 } 291 } 292