1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <asm/mmu.h> 11 #include <asm/immap_85xx.h> 12 #include <asm/processor.h> 13 #include <asm/fsl_ddr_sdram.h> 14 #include <asm/fsl_ddr_dimm_params.h> 15 #include <asm/io.h> 16 #include <asm/fsl_law.h> 17 18 #ifdef CONFIG_SYS_DDR_RAW_TIMING 19 #if defined(CONFIG_P1020RDB_PROTO) || \ 20 defined(CONFIG_P1021RDB) || \ 21 defined(CONFIG_P1020UTM) 22 /* Micron MT41J256M8_187E */ 23 dimm_params_t ddr_raw_timing = { 24 .n_ranks = 1, 25 .rank_density = 1073741824u, 26 .capacity = 1073741824u, 27 .primary_sdram_width = 32, 28 .ec_sdram_width = 0, 29 .registered_dimm = 0, 30 .mirrored_dimm = 0, 31 .n_row_addr = 15, 32 .n_col_addr = 10, 33 .n_banks_per_sdram_device = 8, 34 .edc_config = 0, 35 .burst_lengths_bitmask = 0x0c, 36 37 .tCKmin_X_ps = 1870, 38 .caslat_X = 0x1e << 4, /* 5,6,7,8 */ 39 .tAA_ps = 13125, 40 .tWR_ps = 15000, 41 .tRCD_ps = 13125, 42 .tRRD_ps = 7500, 43 .tRP_ps = 13125, 44 .tRAS_ps = 37500, 45 .tRC_ps = 50625, 46 .tRFC_ps = 160000, 47 .tWTR_ps = 7500, 48 .tRTP_ps = 7500, 49 .refresh_rate_ps = 7800000, 50 .tFAW_ps = 37500, 51 }; 52 #elif defined(CONFIG_P2020RDB) 53 /* Micron MT41J128M16_15E */ 54 dimm_params_t ddr_raw_timing = { 55 .n_ranks = 1, 56 .rank_density = 1073741824u, 57 .capacity = 1073741824u, 58 .primary_sdram_width = 64, 59 .ec_sdram_width = 0, 60 .registered_dimm = 0, 61 .mirrored_dimm = 0, 62 .n_row_addr = 14, 63 .n_col_addr = 10, 64 .n_banks_per_sdram_device = 8, 65 .edc_config = 0, 66 .burst_lengths_bitmask = 0x0c, 67 68 .tCKmin_X_ps = 1500, 69 .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */ 70 .tAA_ps = 13500, 71 .tWR_ps = 15000, 72 .tRCD_ps = 13500, 73 .tRRD_ps = 6000, 74 .tRP_ps = 13500, 75 .tRAS_ps = 36000, 76 .tRC_ps = 49500, 77 .tRFC_ps = 160000, 78 .tWTR_ps = 7500, 79 .tRTP_ps = 7500, 80 .refresh_rate_ps = 7800000, 81 .tFAW_ps = 30000, 82 }; 83 #elif defined(CONFIG_P1020MBG) 84 /* Micron MT41J512M8_187E */ 85 dimm_params_t ddr_raw_timing = { 86 .n_ranks = 2, 87 .rank_density = 1073741824u, 88 .capacity = 2147483648u, 89 .primary_sdram_width = 32, 90 .ec_sdram_width = 0, 91 .registered_dimm = 0, 92 .mirrored_dimm = 0, 93 .n_row_addr = 15, 94 .n_col_addr = 10, 95 .n_banks_per_sdram_device = 8, 96 .edc_config = 0, 97 .burst_lengths_bitmask = 0x0c, 98 99 .tCKmin_X_ps = 1870, 100 .caslat_X = 0x1e << 4, /* 5,6,7,8 */ 101 .tAA_ps = 13125, 102 .tWR_ps = 15000, 103 .tRCD_ps = 13125, 104 .tRRD_ps = 7500, 105 .tRP_ps = 13125, 106 .tRAS_ps = 37500, 107 .tRC_ps = 50625, 108 .tRFC_ps = 160000, 109 .tWTR_ps = 7500, 110 .tRTP_ps = 7500, 111 .refresh_rate_ps = 7800000, 112 .tFAW_ps = 37500, 113 }; 114 #elif defined(CONFIG_P1020RDB) 115 /* 116 * Samsung K4B2G0846C-HCF8 117 * The following timing are for "downshift" 118 * i.e. to use CL9 part as CL7 119 * otherwise, tAA, tRCD, tRP will be 13500ps 120 * and tRC will be 49500ps 121 */ 122 dimm_params_t ddr_raw_timing = { 123 .n_ranks = 1, 124 .rank_density = 1073741824u, 125 .capacity = 1073741824u, 126 .primary_sdram_width = 32, 127 .ec_sdram_width = 0, 128 .registered_dimm = 0, 129 .mirrored_dimm = 0, 130 .n_row_addr = 15, 131 .n_col_addr = 10, 132 .n_banks_per_sdram_device = 8, 133 .edc_config = 0, 134 .burst_lengths_bitmask = 0x0c, 135 136 .tCKmin_X_ps = 1875, 137 .caslat_X = 0x1e << 4, /* 5,6,7,8 */ 138 .tAA_ps = 13125, 139 .tWR_ps = 15000, 140 .tRCD_ps = 13125, 141 .tRRD_ps = 7500, 142 .tRP_ps = 13125, 143 .tRAS_ps = 37500, 144 .tRC_ps = 50625, 145 .tRFC_ps = 160000, 146 .tWTR_ps = 7500, 147 .tRTP_ps = 7500, 148 .refresh_rate_ps = 7800000, 149 .tFAW_ps = 37500, 150 }; 151 #elif defined(CONFIG_P1024RDB) || \ 152 defined(CONFIG_P1025RDB) 153 /* 154 * Samsung K4B2G0846C-HCH9 155 * The following timing are for "downshift" 156 * i.e. to use CL9 part as CL7 157 * otherwise, tAA, tRCD, tRP will be 13500ps 158 * and tRC will be 49500ps 159 */ 160 dimm_params_t ddr_raw_timing = { 161 .n_ranks = 1, 162 .rank_density = 1073741824u, 163 .capacity = 1073741824u, 164 .primary_sdram_width = 32, 165 .ec_sdram_width = 0, 166 .registered_dimm = 0, 167 .mirrored_dimm = 0, 168 .n_row_addr = 15, 169 .n_col_addr = 10, 170 .n_banks_per_sdram_device = 8, 171 .edc_config = 0, 172 .burst_lengths_bitmask = 0x0c, 173 174 .tCKmin_X_ps = 1500, 175 .caslat_X = 0x3e << 4, /* 5,6,7,8,9 */ 176 .tAA_ps = 13125, 177 .tWR_ps = 15000, 178 .tRCD_ps = 13125, 179 .tRRD_ps = 6000, 180 .tRP_ps = 13125, 181 .tRAS_ps = 36000, 182 .tRC_ps = 49125, 183 .tRFC_ps = 160000, 184 .tWTR_ps = 7500, 185 .tRTP_ps = 7500, 186 .refresh_rate_ps = 7800000, 187 .tFAW_ps = 30000, 188 }; 189 #else 190 #error Missing raw timing data for this board 191 #endif 192 193 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 194 unsigned int controller_number, 195 unsigned int dimm_number) 196 { 197 const char dimm_model[] = "Fixed DDR on board"; 198 199 if ((controller_number == 0) && (dimm_number == 0)) { 200 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 201 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 202 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 203 } 204 205 return 0; 206 } 207 #endif /* CONFIG_SYS_DDR_RAW_TIMING */ 208 209 #ifdef CONFIG_SYS_DDR_CS0_BNDS 210 /* Fixed sdram init -- doesn't use serial presence detect. */ 211 phys_size_t fixed_sdram(void) 212 { 213 sys_info_t sysinfo; 214 char buf[32]; 215 size_t ddr_size; 216 fsl_ddr_cfg_regs_t ddr_cfg_regs = { 217 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, 218 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, 219 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, 220 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 221 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, 222 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, 223 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, 224 #endif 225 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, 226 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, 227 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, 228 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, 229 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, 230 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 231 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, 232 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, 233 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, 234 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, 235 .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, 236 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, 237 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, 238 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, 239 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, 240 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 241 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, 242 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, 243 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, 244 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, 245 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 246 }; 247 248 get_sys_info(&sysinfo); 249 printf("Configuring DDR for %s MT/s data rate\n", 250 strmhz(buf, sysinfo.freqDDRBus)); 251 252 ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 253 254 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); 255 256 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, 257 ddr_size, LAW_TRGT_IF_DDR_1) < 0) { 258 printf("ERROR setting Local Access Windows for DDR\n"); 259 return 0; 260 }; 261 262 return ddr_size; 263 } 264 #endif 265 266 void fsl_ddr_board_options(memctl_options_t *popts, 267 dimm_params_t *pdimm, 268 unsigned int ctrl_num) 269 { 270 int i; 271 popts->clk_adjust = 6; 272 popts->cpo_override = 0x1f; 273 popts->write_data_delay = 2; 274 popts->half_strength_driver_enable = 1; 275 /* Write leveling override */ 276 popts->wrlvl_en = 1; 277 popts->wrlvl_override = 1; 278 popts->wrlvl_sample = 0xf; 279 popts->wrlvl_start = 0x8; 280 popts->trwt_override = 1; 281 popts->trwt = 0; 282 283 if (pdimm->primary_sdram_width == 64) 284 popts->data_bus_width = 0; 285 else if (pdimm->primary_sdram_width == 32) 286 popts->data_bus_width = 1; 287 else 288 printf("Error in DDR bus width configuration!\n"); 289 290 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 291 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 292 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 293 } 294 } 295