1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/mmu.h> 8 9 struct fsl_e_tlb_entry tlb_table[] = { 10 /* TLB 0 - for temp stack in cache */ 11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 12 MAS3_SX|MAS3_SW|MAS3_SR, 0, 13 0, 0, BOOKE_PAGESZ_4K, 0), 14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 15 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 16 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 0, 0, BOOKE_PAGESZ_4K, 0), 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 19 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 20 MAS3_SX|MAS3_SW|MAS3_SR, 0, 21 0, 0, BOOKE_PAGESZ_4K, 0), 22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 23 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 24 MAS3_SX|MAS3_SW|MAS3_SR, 0, 25 0, 0, BOOKE_PAGESZ_4K, 0), 26 27 /* TLB 1 */ 28 /* *I*** - Covers boot page */ 29 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 30 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 31 0, 0, BOOKE_PAGESZ_4K, 1), 32 33 /* *I*G* - CCSRBAR */ 34 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 35 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36 0, 1, BOOKE_PAGESZ_4M, 1), 37 38 /* W**G* - Flash, localbus */ 39 /* This will be changed to *I*G* after relocation to RAM. */ 40 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 41 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 42 0, 2, BOOKE_PAGESZ_256M, 1), 43 44 /* *I*G* - PCI */ 45 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, 46 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 47 0, 3, BOOKE_PAGESZ_1G, 1), 48 49 /* *I*G* - PCI */ 50 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, 51 CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, 52 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 53 0, 4, BOOKE_PAGESZ_256M, 1), 54 55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, 56 CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, 57 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 58 0, 5, BOOKE_PAGESZ_256M, 1), 59 60 /* *I*G* - PCI I/O */ 61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, 62 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63 0, 6, BOOKE_PAGESZ_256K, 1), 64 65 /* Bman/Qman */ 66 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 67 MAS3_SW|MAS3_SR, 0, 68 0, 7, BOOKE_PAGESZ_1M, 1), 69 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 70 CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 71 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 72 0, 8, BOOKE_PAGESZ_1M, 1), 73 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 74 MAS3_SW|MAS3_SR, MAS2_M, 75 0, 9, BOOKE_PAGESZ_1M, 1), 76 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 77 CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 78 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 79 0, 10, BOOKE_PAGESZ_1M, 1), 80 81 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 82 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 83 0, 11, BOOKE_PAGESZ_16K, 1), 84 85 #ifdef CONFIG_SYS_RAMBOOT 86 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, 87 CONFIG_SYS_DDR_SDRAM_BASE, 88 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 89 0, 12, BOOKE_PAGESZ_256M, 1), 90 91 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 92 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 93 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 94 0, 13, BOOKE_PAGESZ_256M, 1), 95 #endif 96 }; 97 98 int num_tlb_entries = ARRAY_SIZE(tlb_table); 99