1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/mmu.h> 25 26 struct fsl_e_tlb_entry tlb_table[] = { 27 /* TLB 0 - for temp stack in cache */ 28 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 29 MAS3_SX|MAS3_SW|MAS3_SR, 0, 30 0, 0, BOOKE_PAGESZ_4K, 0), 31 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 32 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 33 MAS3_SX|MAS3_SW|MAS3_SR, 0, 34 0, 0, BOOKE_PAGESZ_4K, 0), 35 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 36 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 37 MAS3_SX|MAS3_SW|MAS3_SR, 0, 38 0, 0, BOOKE_PAGESZ_4K, 0), 39 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 40 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 41 MAS3_SX|MAS3_SW|MAS3_SR, 0, 42 0, 0, BOOKE_PAGESZ_4K, 0), 43 44 /* TLB 1 */ 45 /* *I*** - Covers boot page */ 46 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 47 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 48 0, 0, BOOKE_PAGESZ_4K, 1), 49 50 /* *I*G* - CCSRBAR */ 51 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 52 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 53 0, 1, BOOKE_PAGESZ_4M, 1), 54 55 /* W**G* - Flash, localbus */ 56 /* This will be changed to *I*G* after relocation to RAM. */ 57 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 59 0, 2, BOOKE_PAGESZ_256M, 1), 60 61 /* *I*G* - PCI */ 62 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, 63 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64 0, 3, BOOKE_PAGESZ_1G, 1), 65 66 /* *I*G* - PCI */ 67 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, 68 CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, 69 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 70 0, 4, BOOKE_PAGESZ_256M, 1), 71 72 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, 73 CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, 74 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 75 0, 5, BOOKE_PAGESZ_256M, 1), 76 77 /* *I*G* - PCI I/O */ 78 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, 79 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 80 0, 6, BOOKE_PAGESZ_256K, 1), 81 82 /* Bman/Qman */ 83 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 84 MAS3_SW|MAS3_SR, 0, 85 0, 7, BOOKE_PAGESZ_1M, 1), 86 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 87 CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 88 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 89 0, 8, BOOKE_PAGESZ_1M, 1), 90 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 91 MAS3_SW|MAS3_SR, MAS2_M, 92 0, 9, BOOKE_PAGESZ_1M, 1), 93 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 94 CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 95 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 96 0, 10, BOOKE_PAGESZ_1M, 1), 97 98 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 99 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 100 0, 11, BOOKE_PAGESZ_16K, 1), 101 102 #ifdef CONFIG_SYS_RAMBOOT 103 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, 104 CONFIG_SYS_DDR_SDRAM_BASE, 105 MAS3_SX|MAS3_SW|MAS3_SR, 0, 106 0, 12, BOOKE_PAGESZ_256M, 1), 107 108 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 109 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 110 MAS3_SX|MAS3_SW|MAS3_SR, 0, 111 0, 13, BOOKE_PAGESZ_256M, 1), 112 #endif 113 }; 114 115 int num_tlb_entries = ARRAY_SIZE(tlb_table); 116