1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
5  *           Chunhe Lan <Chunhe.Lan@freescale.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #include <common.h>
11 #include <command.h>
12 #include <pci.h>
13 #include <asm/io.h>
14 #include <asm/cache.h>
15 #include <asm/processor.h>
16 #include <asm/mmu.h>
17 #include <asm/immap_85xx.h>
18 #include <asm/fsl_pci.h>
19 #include <fsl_ddr_sdram.h>
20 #include <asm/fsl_portals.h>
21 #include <libfdt.h>
22 #include <fdt_support.h>
23 #include <netdev.h>
24 #include <malloc.h>
25 #include <fm_eth.h>
26 #include <fsl_mdio.h>
27 #include <miiphy.h>
28 #include <phy.h>
29 #include <asm/fsl_dtsec.h>
30 
31 DECLARE_GLOBAL_DATA_PTR;
32 
33 int board_early_init_f(void)
34 {
35 	fsl_lbc_t *lbc = LBC_BASE_ADDR;
36 
37 	/* Set ABSWP to implement conversion of addresses in the LBC */
38 	setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
39 
40 	return 0;
41 }
42 
43 int checkboard(void)
44 {
45 	printf("Board: P1023 RDB\n");
46 
47 	return 0;
48 }
49 
50 #ifdef CONFIG_PCI
51 void pci_init_board(void)
52 {
53 	fsl_pcie_init_board(0);
54 }
55 #endif
56 
57 int board_early_init_r(void)
58 {
59 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
60 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
61 
62 	/*
63 	 * Remap Boot flash + PROMJET region to caching-inhibited
64 	 * so that flash can be erased properly.
65 	 */
66 
67 	/* Flush d-cache and invalidate i-cache of any FLASH data */
68 	flush_dcache();
69 	invalidate_icache();
70 
71 	/* invalidate existing TLB entry for flash + promjet */
72 	disable_tlb(flash_esel);
73 
74 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
75 		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
76 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
77 
78 	setup_portals();
79 
80 	return 0;
81 }
82 
83 unsigned long get_board_sys_clk(ulong dummy)
84 {
85 	return gd->bus_clk;
86 }
87 
88 unsigned long get_board_ddr_clk(ulong dummy)
89 {
90 	return gd->mem_clk;
91 }
92 
93 int board_eth_init(bd_t *bis)
94 {
95 	ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
96 	struct fsl_pq_mdio_info dtsec_mdio_info;
97 
98 	/*
99 	 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
100 	 * is not correct.
101 	 */
102 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
103 
104 	dtsec_mdio_info.regs =
105 		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
106 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
107 
108 	/* Register the 1G MDIO bus */
109 	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
110 
111 	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
112 	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
113 
114 	fm_info_set_mdio(FM1_DTSEC1,
115 			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
116 	fm_info_set_mdio(FM1_DTSEC2,
117 			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
118 
119 #ifdef CONFIG_FMAN_ENET
120 	cpu_eth_init(bis);
121 #endif
122 
123 	return pci_eth_init(bis);
124 }
125 
126 #if defined(CONFIG_OF_BOARD_SETUP)
127 void ft_board_setup(void *blob, bd_t *bd)
128 {
129 	phys_addr_t base;
130 	phys_size_t size;
131 
132 	ft_cpu_setup(blob, bd);
133 
134 	base = getenv_bootm_low();
135 	size = getenv_bootm_size();
136 
137 	fdt_fixup_memory(blob, (u64)base, (u64)size);
138 
139 #ifdef CONFIG_HAS_FSL_DR_USB
140 	fdt_fixup_dr_usb(blob, bd);
141 #endif
142 
143 	fdt_fixup_fman_ethernet(blob);
144 }
145 #endif
146