1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/mmu.h> 9 #include <asm/immap_85xx.h> 10 #include <asm/processor.h> 11 #include <fsl_ddr_sdram.h> 12 #include <fsl_ddr_dimm_params.h> 13 #include <asm/io.h> 14 #include <asm/fsl_law.h> 15 16 /* CONFIG_SYS_DDR_RAW_TIMING */ 17 /* 18 * Hynix H5TQ1G83TFR-H9C 19 */ 20 dimm_params_t ddr_raw_timing = { 21 .n_ranks = 1, 22 .rank_density = 536870912u, 23 .capacity = 536870912u, 24 .primary_sdram_width = 32, 25 .ec_sdram_width = 0, 26 .registered_dimm = 0, 27 .mirrored_dimm = 0, 28 .n_row_addr = 14, 29 .n_col_addr = 10, 30 .n_banks_per_sdram_device = 8, 31 .edc_config = 0, 32 .burst_lengths_bitmask = 0x0c, 33 34 .tckmin_x_ps = 1875, 35 .caslat_x = 0x1e << 4, /* 5,6,7,8 */ 36 .taa_ps = 13125, 37 .twr_ps = 18000, 38 .trcd_ps = 13125, 39 .trrd_ps = 7500, 40 .trp_ps = 13125, 41 .tras_ps = 37500, 42 .trc_ps = 50625, 43 .trfc_ps = 160000, 44 .twtr_ps = 7500, 45 .trtp_ps = 7500, 46 .refresh_rate_ps = 7800000, 47 .tfaw_ps = 37500, 48 }; 49 50 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 51 unsigned int controller_number, 52 unsigned int dimm_number) 53 { 54 const char dimm_model[] = "Fixed DDR on board"; 55 56 if ((controller_number == 0) && (dimm_number == 0)) { 57 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 58 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 59 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 60 } 61 62 return 0; 63 } 64 65 void fsl_ddr_board_options(memctl_options_t *popts, 66 dimm_params_t *pdimm, 67 unsigned int ctrl_num) 68 { 69 int i; 70 popts->clk_adjust = 6; 71 popts->cpo_override = 0x1f; 72 popts->write_data_delay = 2; 73 popts->half_strength_driver_enable = 1; 74 /* Write leveling override */ 75 popts->wrlvl_en = 1; 76 popts->wrlvl_override = 1; 77 popts->wrlvl_sample = 0xf; 78 popts->wrlvl_start = 0x8; 79 popts->trwt_override = 1; 80 popts->trwt = 0; 81 82 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 83 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 84 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 85 } 86 } 87