1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2010 Freescale Semiconductor, Inc. 4 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 5 * Timur Tabi <timur@freescale.com> 6 */ 7 8 #include <common.h> 9 #include <asm/mmu.h> 10 11 struct fsl_e_tlb_entry tlb_table[] = { 12 /* TLB 0 - for temp stack in cache */ 13 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 14 MAS3_SX|MAS3_SW|MAS3_SR, 0, 15 0, 0, BOOKE_PAGESZ_4K, 0), 16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 18 MAS3_SX|MAS3_SW|MAS3_SR, 0, 19 0, 0, BOOKE_PAGESZ_4K, 0), 20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22 MAS3_SX|MAS3_SW|MAS3_SR, 0, 23 0, 0, BOOKE_PAGESZ_4K, 0), 24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 26 MAS3_SX|MAS3_SW|MAS3_SR, 0, 27 0, 0, BOOKE_PAGESZ_4K, 0), 28 29 /* TLB 1 */ 30 /* *I*** - Covers boot page */ 31 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 32 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 33 0, 0, BOOKE_PAGESZ_4K, 1), 34 35 /* *I*G* - CCSRBAR */ 36 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 37 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 38 0, 1, BOOKE_PAGESZ_1M, 1), 39 40 #ifndef CONFIG_SPL_BUILD 41 /* W**G* - Flash/promjet, localbus */ 42 /* This will be changed to *I*G* after relocation to RAM. */ 43 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 44 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 45 0, 2, BOOKE_PAGESZ_256M, 1), 46 47 /* *I*G* - PCI */ 48 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, 49 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 50 0, 3, BOOKE_PAGESZ_1G, 1), 51 52 /* *I*G* - PCI */ 53 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, 54 CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, 55 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 56 0, 4, BOOKE_PAGESZ_256M, 1), 57 58 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, 59 CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, 60 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61 0, 5, BOOKE_PAGESZ_256M, 1), 62 63 /* *I*G* - PCI I/O */ 64 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, 65 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 66 0, 6, BOOKE_PAGESZ_256K, 1), 67 #endif 68 69 SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, 70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 71 0, 7, BOOKE_PAGESZ_4K, 1), 72 73 #if defined(CONFIG_SYS_RAMBOOT) || \ 74 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) 75 /* **** - eSDHC/eSPI/NAND boot */ 76 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 77 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 78 0, 8, BOOKE_PAGESZ_1G, 1), 79 /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ 80 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 81 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 82 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 83 0, 9, BOOKE_PAGESZ_1G, 1), 84 #endif 85 86 #ifdef CONFIG_SYS_NAND_BASE 87 /* *I*G - NAND */ 88 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 89 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 90 0, 10, BOOKE_PAGESZ_16K, 1), 91 #endif 92 93 #ifdef CONFIG_SYS_INIT_L2_ADDR 94 /* *I*G - L2SRAM */ 95 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 96 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 97 0, 11, BOOKE_PAGESZ_256K, 1) 98 #endif 99 }; 100 101 int num_tlb_entries = ARRAY_SIZE(tlb_table); 102