1 /* 2 * Copyright 2010 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/mmu.h> 11 12 struct fsl_e_tlb_entry tlb_table[] = { 13 /* TLB 0 - for temp stack in cache */ 14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 15 MAS3_SX|MAS3_SW|MAS3_SR, 0, 16 0, 0, BOOKE_PAGESZ_4K, 0), 17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 18 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19 MAS3_SX|MAS3_SW|MAS3_SR, 0, 20 0, 0, BOOKE_PAGESZ_4K, 0), 21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23 MAS3_SX|MAS3_SW|MAS3_SR, 0, 24 0, 0, BOOKE_PAGESZ_4K, 0), 25 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 26 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27 MAS3_SX|MAS3_SW|MAS3_SR, 0, 28 0, 0, BOOKE_PAGESZ_4K, 0), 29 30 /* TLB 1 */ 31 /* *I*** - Covers boot page */ 32 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 33 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 34 0, 0, BOOKE_PAGESZ_4K, 1), 35 36 /* *I*G* - CCSRBAR */ 37 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 38 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39 0, 1, BOOKE_PAGESZ_1M, 1), 40 41 #ifndef CONFIG_SPL_BUILD 42 /* W**G* - Flash/promjet, localbus */ 43 /* This will be changed to *I*G* after relocation to RAM. */ 44 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 45 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 46 0, 2, BOOKE_PAGESZ_256M, 1), 47 48 /* *I*G* - PCI */ 49 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, 50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51 0, 3, BOOKE_PAGESZ_1G, 1), 52 53 /* *I*G* - PCI */ 54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, 55 CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, 56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57 0, 4, BOOKE_PAGESZ_256M, 1), 58 59 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, 60 CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, 61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62 0, 5, BOOKE_PAGESZ_256M, 1), 63 64 /* *I*G* - PCI I/O */ 65 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67 0, 6, BOOKE_PAGESZ_256K, 1), 68 #endif 69 70 SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, 71 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 72 0, 7, BOOKE_PAGESZ_4K, 1), 73 74 #if defined(CONFIG_SYS_RAMBOOT) || \ 75 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) 76 /* **** - eSDHC/eSPI/NAND boot */ 77 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 78 MAS3_SX|MAS3_SW|MAS3_SR, 0, 79 0, 8, BOOKE_PAGESZ_1G, 1), 80 /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ 81 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 82 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 83 MAS3_SX|MAS3_SW|MAS3_SR, 0, 84 0, 9, BOOKE_PAGESZ_1G, 1), 85 #endif 86 87 #ifdef CONFIG_SYS_NAND_BASE 88 /* *I*G - NAND */ 89 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 90 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 91 0, 10, BOOKE_PAGESZ_16K, 1), 92 #endif 93 94 #ifdef CONFIG_SYS_INIT_L2_ADDR 95 /* *I*G - L2SRAM */ 96 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 97 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 98 0, 11, BOOKE_PAGESZ_256K, 1) 99 #endif 100 }; 101 102 int num_tlb_entries = ARRAY_SIZE(tlb_table); 103