1*f45210d6SMatthew McClintock /* 2*f45210d6SMatthew McClintock * Copyright 2011 Freescale Semiconductor, Inc. 3*f45210d6SMatthew McClintock * 4*f45210d6SMatthew McClintock * This program is free software; you can redistribute it and/or 5*f45210d6SMatthew McClintock * modify it under the terms of the GNU General Public License as 6*f45210d6SMatthew McClintock * published by the Free Software Foundation; either version 2 of 7*f45210d6SMatthew McClintock * the License, or (at your option) any later version. 8*f45210d6SMatthew McClintock * 9*f45210d6SMatthew McClintock * This program is distributed in the hope that it will be useful, 10*f45210d6SMatthew McClintock * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*f45210d6SMatthew McClintock * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*f45210d6SMatthew McClintock * 13*f45210d6SMatthew McClintock * GNU General Public License for more details. 14*f45210d6SMatthew McClintock * 15*f45210d6SMatthew McClintock * You should have received a copy of the GNU General Public License 16*f45210d6SMatthew McClintock * along with this program; if not, write to the Free Software 17*f45210d6SMatthew McClintock * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18*f45210d6SMatthew McClintock * MA 02111-1307 USA 19*f45210d6SMatthew McClintock * 20*f45210d6SMatthew McClintock */ 21*f45210d6SMatthew McClintock 22*f45210d6SMatthew McClintock #include <common.h> 23*f45210d6SMatthew McClintock #include <ns16550.h> 24*f45210d6SMatthew McClintock #include <asm/io.h> 25*f45210d6SMatthew McClintock #include <nand.h> 26*f45210d6SMatthew McClintock #include <asm/fsl_law.h> 27*f45210d6SMatthew McClintock #include <asm/fsl_ddr_sdram.h> 28*f45210d6SMatthew McClintock 29*f45210d6SMatthew McClintock 30*f45210d6SMatthew McClintock /* 31*f45210d6SMatthew McClintock * Fixed sdram init -- doesn't use serial presence detect. 32*f45210d6SMatthew McClintock */ 33*f45210d6SMatthew McClintock void sdram_init(void) 34*f45210d6SMatthew McClintock { 35*f45210d6SMatthew McClintock volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; 36*f45210d6SMatthew McClintock 37*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); 38*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); 39*f45210d6SMatthew McClintock #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 40*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); 41*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); 42*f45210d6SMatthew McClintock #endif 43*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); 44*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); 45*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); 46*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); 47*f45210d6SMatthew McClintock 48*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); 49*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); 50*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); 51*f45210d6SMatthew McClintock 52*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); 53*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); 54*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); 55*f45210d6SMatthew McClintock 56*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); 57*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); 58*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); 59*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); 60*f45210d6SMatthew McClintock 61*f45210d6SMatthew McClintock /* Set, but do not enable the memory */ 62*f45210d6SMatthew McClintock __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, 63*f45210d6SMatthew McClintock &ddr->sdram_cfg); 64*f45210d6SMatthew McClintock 65*f45210d6SMatthew McClintock in_be32(&ddr->sdram_cfg); 66*f45210d6SMatthew McClintock udelay(500); 67*f45210d6SMatthew McClintock 68*f45210d6SMatthew McClintock /* Let the controller go */ 69*f45210d6SMatthew McClintock out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); 70*f45210d6SMatthew McClintock in_be32(&ddr->sdram_cfg); 71*f45210d6SMatthew McClintock 72*f45210d6SMatthew McClintock set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); 73*f45210d6SMatthew McClintock } 74*f45210d6SMatthew McClintock 75*f45210d6SMatthew McClintock const static u32 sysclk_tbl[] = { 76*f45210d6SMatthew McClintock 66666000, 7499900, 83332500, 8999900, 77*f45210d6SMatthew McClintock 99999000, 11111000, 12499800, 13333200 78*f45210d6SMatthew McClintock }; 79*f45210d6SMatthew McClintock 80*f45210d6SMatthew McClintock void board_init_f(ulong bootflag) 81*f45210d6SMatthew McClintock { 82*f45210d6SMatthew McClintock int px_spd; 83*f45210d6SMatthew McClintock u32 plat_ratio, sys_clk, bus_clk; 84*f45210d6SMatthew McClintock ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 85*f45210d6SMatthew McClintock 86*f45210d6SMatthew McClintock /* for FPGA */ 87*f45210d6SMatthew McClintock set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 88*f45210d6SMatthew McClintock set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 89*f45210d6SMatthew McClintock 90*f45210d6SMatthew McClintock /* initialize selected port with appropriate baud rate */ 91*f45210d6SMatthew McClintock px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); 92*f45210d6SMatthew McClintock sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; 93*f45210d6SMatthew McClintock plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 94*f45210d6SMatthew McClintock bus_clk = sys_clk * plat_ratio / 2; 95*f45210d6SMatthew McClintock 96*f45210d6SMatthew McClintock NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 97*f45210d6SMatthew McClintock bus_clk / 16 / CONFIG_BAUDRATE); 98*f45210d6SMatthew McClintock 99*f45210d6SMatthew McClintock puts("\nNAND boot... "); 100*f45210d6SMatthew McClintock 101*f45210d6SMatthew McClintock /* Initialize the DDR3 */ 102*f45210d6SMatthew McClintock sdram_init(); 103*f45210d6SMatthew McClintock 104*f45210d6SMatthew McClintock /* copy code to RAM and jump to it - this should not return */ 105*f45210d6SMatthew McClintock /* NOTE - code has to be copied out of NAND buffer before 106*f45210d6SMatthew McClintock * other blocks can be read. 107*f45210d6SMatthew McClintock */ 108*f45210d6SMatthew McClintock relocate_code(CONFIG_SPL_RELOC_STACK, 0, 109*f45210d6SMatthew McClintock CONFIG_SPL_RELOC_TEXT_BASE); 110*f45210d6SMatthew McClintock } 111*f45210d6SMatthew McClintock 112*f45210d6SMatthew McClintock void board_init_r(gd_t *gd, ulong dest_addr) 113*f45210d6SMatthew McClintock { 114*f45210d6SMatthew McClintock nand_boot(); 115*f45210d6SMatthew McClintock } 116*f45210d6SMatthew McClintock 117*f45210d6SMatthew McClintock void putc(char c) 118*f45210d6SMatthew McClintock { 119*f45210d6SMatthew McClintock if (c == '\n') 120*f45210d6SMatthew McClintock NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); 121*f45210d6SMatthew McClintock 122*f45210d6SMatthew McClintock NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); 123*f45210d6SMatthew McClintock } 124*f45210d6SMatthew McClintock 125*f45210d6SMatthew McClintock void puts(const char *str) 126*f45210d6SMatthew McClintock { 127*f45210d6SMatthew McClintock while (*str) 128*f45210d6SMatthew McClintock putc(*str++); 129*f45210d6SMatthew McClintock } 130