1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 */ 11 12 #include <common.h> 13 #include <command.h> 14 #include <pci.h> 15 #include <asm/processor.h> 16 #include <asm/mmu.h> 17 #include <asm/cache.h> 18 #include <asm/immap_85xx.h> 19 #include <asm/fsl_pci.h> 20 #include <asm/fsl_ddr_sdram.h> 21 #include <asm/fsl_serdes.h> 22 #include <asm/io.h> 23 #include <libfdt.h> 24 #include <fdt_support.h> 25 #include <tsec.h> 26 #include <asm/fsl_law.h> 27 #include <netdev.h> 28 #include <i2c.h> 29 #include <hwconfig.h> 30 31 #include "../common/ngpixis.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 int board_early_init_f(void) 36 { 37 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 38 39 /* Set pmuxcr to allow both i2c1 and i2c2 */ 40 setbits_be32(&gur->pmuxcr, 0x1000); 41 42 /* Read back the register to synchronize the write. */ 43 in_be32(&gur->pmuxcr); 44 45 /* Set the pin muxing to enable ETSEC2. */ 46 clrbits_be32(&gur->pmuxcr2, 0x001F8000); 47 48 return 0; 49 } 50 51 int checkboard(void) 52 { 53 u8 sw; 54 55 puts("Board: P1022DS "); 56 #ifdef CONFIG_PHYS_64BIT 57 puts("(36-bit addrmap) "); 58 #endif 59 60 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 61 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 62 63 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 64 65 switch ((sw & PIXIS_LBMAP_MASK) >> 6) { 66 case 0: 67 printf ("vBank: %u\n", ((sw & 0x30) >> 4)); 68 break; 69 case 1: 70 printf ("NAND\n"); 71 break; 72 case 2: 73 case 3: 74 puts ("Promjet\n"); 75 break; 76 } 77 78 return 0; 79 } 80 81 #define CONFIG_TFP410_I2C_ADDR 0x38 82 83 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ 84 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c 85 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03 86 87 /* Route the I2C1 pins to the SSI port instead. */ 88 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08 89 90 /* Choose the 12.288Mhz codec reference clock */ 91 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02 92 93 /* Choose the 11.2896Mhz codec reference clock */ 94 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 95 96 /* Connect to USB2 */ 97 #define CONFIG_PIXIS_BRDCFG0_USB2 0x10 98 /* Connect to TFM bus */ 99 #define CONFIG_PIXIS_BRDCFG1_TDM 0x0c 100 /* Connect to SPI */ 101 #define CONFIG_PIXIS_BRDCFG0_SPI 0x80 102 103 int misc_init_r(void) 104 { 105 u8 temp; 106 const char *audclk; 107 size_t arglen; 108 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 109 110 /* For DVI, enable the TFP410 Encoder. */ 111 112 temp = 0xBF; 113 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) 114 return -1; 115 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) 116 return -1; 117 debug("DVI Encoder Read: 0x%02x\n", temp); 118 119 temp = 0x10; 120 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) 121 return -1; 122 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) 123 return -1; 124 debug("DVI Encoder Read: 0x%02x\n",temp); 125 126 /* Enable the USB2 in PMUXCR2 and FGPA */ 127 if (hwconfig("usb2")) { 128 clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK, 129 MPC85xx_PMUXCR2_USB); 130 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2); 131 } 132 133 /* tdm and audio can not enable simultaneous*/ 134 if (hwconfig("tdm") && hwconfig("audclk")){ 135 printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n"); 136 return -1; 137 } 138 139 /* Enable the TDM in PMUXCR and FGPA */ 140 if (hwconfig("tdm")) { 141 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK, 142 MPC85xx_PMUXCR_TDM); 143 setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM); 144 /* TDM need some configration option by SPI */ 145 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK, 146 MPC85xx_PMUXCR_SPI); 147 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI); 148 } 149 150 /* 151 * Enable the reference clock for the WM8776 codec, and route the MUX 152 * pins for SSI. The default is the 12.288 MHz clock 153 */ 154 155 if (hwconfig("audclk")) { 156 temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | 157 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); 158 temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; 159 160 audclk = hwconfig_arg("audclk", &arglen); 161 /* Check the first two chars only */ 162 if (audclk && (strncmp(audclk, "11", 2) == 0)) 163 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; 164 else 165 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; 166 setbits_8(&pixis->brdcfg1, temp); 167 } 168 169 return 0; 170 } 171 172 /* 173 * A list of PCI and SATA slots 174 */ 175 enum slot_id { 176 SLOT_PCIE1 = 1, 177 SLOT_PCIE2, 178 SLOT_PCIE3, 179 SLOT_PCIE4, 180 SLOT_PCIE5, 181 SLOT_SATA1, 182 SLOT_SATA2 183 }; 184 185 /* 186 * This array maps the slot identifiers to their names on the P1022DS board. 187 */ 188 static const char *slot_names[] = { 189 [SLOT_PCIE1] = "Slot 1", 190 [SLOT_PCIE2] = "Slot 2", 191 [SLOT_PCIE3] = "Slot 3", 192 [SLOT_PCIE4] = "Slot 4", 193 [SLOT_PCIE5] = "Mini-PCIe", 194 [SLOT_SATA1] = "SATA 1", 195 [SLOT_SATA2] = "SATA 2", 196 }; 197 198 /* 199 * This array maps a given SERDES configuration and SERDES device to the PCI or 200 * SATA slot that it connects to. This mapping is hard-coded in the FPGA. 201 */ 202 static u8 serdes_dev_slot[][SATA2 + 1] = { 203 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, 204 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 205 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, 206 [PCIE2] = SLOT_PCIE5 }, 207 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 208 [PCIE2] = SLOT_PCIE3, 209 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 210 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 211 [PCIE2] = SLOT_PCIE3 }, 212 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, 213 [PCIE2] = SLOT_PCIE3, 214 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 215 [0x1c] = { [PCIE1] = SLOT_PCIE1, 216 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 217 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, 218 [0x1f] = { [PCIE1] = SLOT_PCIE1 }, 219 }; 220 221 222 /* 223 * Returns the name of the slot to which the PCIe or SATA controller is 224 * connected 225 */ 226 const char *board_serdes_name(enum srds_prtcl device) 227 { 228 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 229 u32 pordevsr = in_be32(&gur->pordevsr); 230 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 231 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 232 enum slot_id slot = serdes_dev_slot[srds_cfg][device]; 233 const char *name = slot_names[slot]; 234 235 if (name) 236 return name; 237 else 238 return "Nothing"; 239 } 240 241 #ifdef CONFIG_PCI 242 void pci_init_board(void) 243 { 244 fsl_pcie_init_board(0); 245 } 246 #endif 247 248 int board_early_init_r(void) 249 { 250 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 251 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 252 253 /* 254 * Remap Boot flash + PROMJET region to caching-inhibited 255 * so that flash can be erased properly. 256 */ 257 258 /* Flush d-cache and invalidate i-cache of any FLASH data */ 259 flush_dcache(); 260 invalidate_icache(); 261 262 /* invalidate existing TLB entry for flash + promjet */ 263 disable_tlb(flash_esel); 264 265 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 266 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 267 0, flash_esel, BOOKE_PAGESZ_256M, 1); 268 269 return 0; 270 } 271 272 /* 273 * Initialize on-board and/or PCI Ethernet devices 274 * 275 * Returns: 276 * <0, error 277 * 0, no ethernet devices found 278 * >0, number of ethernet devices initialized 279 */ 280 int board_eth_init(bd_t *bis) 281 { 282 struct tsec_info_struct tsec_info[2]; 283 unsigned int num = 0; 284 285 #ifdef CONFIG_TSEC1 286 SET_STD_TSEC_INFO(tsec_info[num], 1); 287 num++; 288 #endif 289 #ifdef CONFIG_TSEC2 290 SET_STD_TSEC_INFO(tsec_info[num], 2); 291 num++; 292 #endif 293 294 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); 295 } 296 297 #ifdef CONFIG_OF_BOARD_SETUP 298 /** 299 * ft_codec_setup - fix up the clock-frequency property of the codec node 300 * 301 * Update the clock-frequency property based on the value of the 'audclk' 302 * hwconfig option. If audclk is not specified, then default to 12.288MHz. 303 */ 304 static void ft_codec_setup(void *blob, const char *compatible) 305 { 306 const char *audclk; 307 size_t arglen; 308 u32 freq; 309 310 audclk = hwconfig_arg("audclk", &arglen); 311 if (audclk && (strncmp(audclk, "11", 2) == 0)) 312 freq = 11289600; 313 else 314 freq = 12288000; 315 316 do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1); 317 } 318 319 void ft_board_setup(void *blob, bd_t *bd) 320 { 321 phys_addr_t base; 322 phys_size_t size; 323 324 ft_cpu_setup(blob, bd); 325 326 base = getenv_bootm_low(); 327 size = getenv_bootm_size(); 328 329 fdt_fixup_memory(blob, (u64)base, (u64)size); 330 331 FT_FSL_PCI_SETUP; 332 333 #ifdef CONFIG_FSL_SGMII_RISER 334 fsl_sgmii_riser_fdt_fixup(blob); 335 #endif 336 337 /* Update the WM8776 node's clock frequency property */ 338 ft_codec_setup(blob, "wlf,wm8776"); 339 } 340 #endif 341