1 /* 2 * Copyright 2010 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 */ 11 12 #include <common.h> 13 #include <command.h> 14 #include <pci.h> 15 #include <asm/processor.h> 16 #include <asm/mmu.h> 17 #include <asm/cache.h> 18 #include <asm/immap_85xx.h> 19 #include <asm/fsl_pci.h> 20 #include <asm/fsl_ddr_sdram.h> 21 #include <asm/fsl_serdes.h> 22 #include <asm/io.h> 23 #include <libfdt.h> 24 #include <fdt_support.h> 25 #include <tsec.h> 26 #include <asm/fsl_law.h> 27 #include <asm/mp.h> 28 #include <netdev.h> 29 #include <i2c.h> 30 #include <hwconfig.h> 31 32 #include "../common/ngpixis.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 int board_early_init_f(void) 37 { 38 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 39 40 /* Set pmuxcr to allow both i2c1 and i2c2 */ 41 setbits_be32(&gur->pmuxcr, 0x1000); 42 43 /* Read back the register to synchronize the write. */ 44 in_be32(&gur->pmuxcr); 45 46 /* Set the pin muxing to enable ETSEC2. */ 47 clrbits_be32(&gur->pmuxcr2, 0x001F8000); 48 49 return 0; 50 } 51 52 int checkboard(void) 53 { 54 u8 sw; 55 56 puts("Board: P1022DS "); 57 58 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 59 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 60 61 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 62 63 switch ((sw & PIXIS_LBMAP_MASK) >> 6) { 64 case 0: 65 printf ("vBank: %u\n", ((sw & 0x30) >> 4)); 66 break; 67 case 1: 68 printf ("NAND\n"); 69 break; 70 case 2: 71 case 3: 72 puts ("Promjet\n"); 73 break; 74 } 75 76 return 0; 77 } 78 79 phys_size_t initdram(int board_type) 80 { 81 phys_size_t dram_size = 0; 82 83 puts("Initializing....\n"); 84 85 dram_size = fsl_ddr_sdram(); 86 dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000; 87 88 puts(" DDR: "); 89 return dram_size; 90 } 91 92 #define CONFIG_TFP410_I2C_ADDR 0x38 93 94 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ 95 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c 96 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03 97 98 /* Route the I2C1 pins to the SSI port instead. */ 99 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08 100 101 /* Choose the 12.288Mhz codec reference clock */ 102 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02 103 104 /* Choose the 11.2896Mhz codec reference clock */ 105 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 106 107 int misc_init_r(void) 108 { 109 u8 temp; 110 const char *audclk; 111 size_t arglen; 112 113 /* For DVI, enable the TFP410 Encoder. */ 114 115 temp = 0xBF; 116 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) 117 return -1; 118 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) 119 return -1; 120 debug("DVI Encoder Read: 0x%02x\n", temp); 121 122 temp = 0x10; 123 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) 124 return -1; 125 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) 126 return -1; 127 debug("DVI Encoder Read: 0x%02x\n",temp); 128 129 /* 130 * Enable the reference clock for the WM8776 codec, and route the MUX 131 * pins for SSI. The default is the 12.288 MHz clock 132 */ 133 134 temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | 135 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); 136 temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; 137 138 audclk = hwconfig_arg("audclk", &arglen); 139 /* Check the first two chars only */ 140 if (audclk && (strncmp(audclk, "11", 2) == 0)) 141 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; 142 else 143 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; 144 out_8(&pixis->brdcfg1, temp); 145 146 return 0; 147 } 148 149 /* 150 * A list of PCI and SATA slots 151 */ 152 enum slot_id { 153 SLOT_PCIE1 = 1, 154 SLOT_PCIE2, 155 SLOT_PCIE3, 156 SLOT_PCIE4, 157 SLOT_PCIE5, 158 SLOT_SATA1, 159 SLOT_SATA2 160 }; 161 162 /* 163 * This array maps the slot identifiers to their names on the P1022DS board. 164 */ 165 static const char *slot_names[] = { 166 [SLOT_PCIE1] = "Slot 1", 167 [SLOT_PCIE2] = "Slot 2", 168 [SLOT_PCIE3] = "Slot 3", 169 [SLOT_PCIE4] = "Slot 4", 170 [SLOT_PCIE5] = "Mini-PCIe", 171 [SLOT_SATA1] = "SATA 1", 172 [SLOT_SATA2] = "SATA 2", 173 }; 174 175 /* 176 * This array maps a given SERDES configuration and SERDES device to the PCI or 177 * SATA slot that it connects to. This mapping is hard-coded in the FPGA. 178 */ 179 static u8 serdes_dev_slot[][SATA2 + 1] = { 180 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, 181 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 182 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, 183 [PCIE2] = SLOT_PCIE5 }, 184 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 185 [PCIE2] = SLOT_PCIE3, 186 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 187 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 188 [PCIE2] = SLOT_PCIE3 }, 189 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, 190 [PCIE2] = SLOT_PCIE3, 191 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 192 [0x1c] = { [PCIE1] = SLOT_PCIE1, 193 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 194 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, 195 [0x1f] = { [PCIE1] = SLOT_PCIE1 }, 196 }; 197 198 199 /* 200 * Returns the name of the slot to which the PCIe or SATA controller is 201 * connected 202 */ 203 const char *serdes_slot_name(enum srds_prtcl device) 204 { 205 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 206 u32 pordevsr = in_be32(&gur->pordevsr); 207 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 208 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 209 enum slot_id slot = serdes_dev_slot[srds_cfg][device]; 210 const char *name = slot_names[slot]; 211 212 if (name) 213 return name; 214 else 215 return "Nothing"; 216 } 217 218 static void configure_pcie(struct fsl_pci_info *info, 219 struct pci_controller *hose, 220 const char *connected) 221 { 222 static int bus_number = 0; 223 int is_endpoint; 224 225 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); 226 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); 227 is_endpoint = fsl_setup_hose(hose, info->regs); 228 printf("PCIE%u: connected to %s as %s (base addr %lx)\n", 229 info->pci_num, connected, 230 is_endpoint ? "Endpoint" : "Root Complex", info->regs); 231 bus_number = fsl_pci_init_port(info, hose, bus_number); 232 } 233 234 #ifdef CONFIG_PCIE1 235 static struct pci_controller pcie1_hose; 236 #endif 237 238 #ifdef CONFIG_PCIE2 239 static struct pci_controller pcie2_hose; 240 #endif 241 242 #ifdef CONFIG_PCIE3 243 static struct pci_controller pcie3_hose; 244 #endif 245 246 #ifdef CONFIG_PCI 247 void pci_init_board(void) 248 { 249 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 250 struct fsl_pci_info pci_info; 251 u32 devdisr = in_be32(&gur->devdisr); 252 253 #ifdef CONFIG_PCIE1 254 if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) { 255 SET_STD_PCIE_INFO(pci_info, 1); 256 configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1)); 257 } else { 258 printf("PCIE1: disabled\n"); 259 } 260 #else 261 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 262 #endif 263 264 #ifdef CONFIG_PCIE2 265 if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { 266 SET_STD_PCIE_INFO(pci_info, 2); 267 configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2)); 268 } else { 269 printf("PCIE2: disabled\n"); 270 } 271 #else 272 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 273 #endif 274 275 #ifdef CONFIG_PCIE3 276 if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { 277 SET_STD_PCIE_INFO(pci_info, 3); 278 configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3)); 279 } else { 280 printf("PCIE3: disabled\n"); 281 } 282 #else 283 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 284 #endif 285 } 286 #endif 287 288 int board_early_init_r(void) 289 { 290 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 291 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 292 293 /* 294 * Remap Boot flash + PROMJET region to caching-inhibited 295 * so that flash can be erased properly. 296 */ 297 298 /* Flush d-cache and invalidate i-cache of any FLASH data */ 299 flush_dcache(); 300 invalidate_icache(); 301 302 /* invalidate existing TLB entry for flash + promjet */ 303 disable_tlb(flash_esel); 304 305 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 306 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 307 0, flash_esel, BOOKE_PAGESZ_256M, 1); 308 309 return 0; 310 } 311 312 /* 313 * Initialize on-board and/or PCI Ethernet devices 314 * 315 * Returns: 316 * <0, error 317 * 0, no ethernet devices found 318 * >0, number of ethernet devices initialized 319 */ 320 int board_eth_init(bd_t *bis) 321 { 322 struct tsec_info_struct tsec_info[2]; 323 unsigned int num = 0; 324 325 #ifdef CONFIG_TSEC1 326 SET_STD_TSEC_INFO(tsec_info[num], 1); 327 num++; 328 #endif 329 #ifdef CONFIG_TSEC2 330 SET_STD_TSEC_INFO(tsec_info[num], 2); 331 num++; 332 #endif 333 334 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); 335 } 336 337 #ifdef CONFIG_OF_BOARD_SETUP 338 /** 339 * ft_codec_setup - fix up the clock-frequency property of the codec node 340 * 341 * Update the clock-frequency property based on the value of the 'audclk' 342 * hwconfig option. If audclk is not specified, then default to 12.288MHz. 343 */ 344 static void ft_codec_setup(void *blob, const char *compatible) 345 { 346 const char *audclk; 347 size_t arglen; 348 u32 freq; 349 350 audclk = hwconfig_arg("audclk", &arglen); 351 if (audclk && (strncmp(audclk, "11", 2) == 0)) 352 freq = 11289600; 353 else 354 freq = 12288000; 355 356 do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1); 357 } 358 359 void ft_board_setup(void *blob, bd_t *bd) 360 { 361 phys_addr_t base; 362 phys_size_t size; 363 364 ft_cpu_setup(blob, bd); 365 366 base = getenv_bootm_low(); 367 size = getenv_bootm_size(); 368 369 fdt_fixup_memory(blob, (u64)base, (u64)size); 370 371 FT_FSL_PCI_SETUP; 372 373 #ifdef CONFIG_FSL_SGMII_RISER 374 fsl_sgmii_riser_fdt_fixup(blob); 375 #endif 376 377 /* Update the WM8776 node's clock frequency property */ 378 ft_codec_setup(blob, "wlf,wm8776"); 379 } 380 #endif 381 382 #ifdef CONFIG_MP 383 void board_lmb_reserve(struct lmb *lmb) 384 { 385 cpu_mp_lmb_reserve(lmb); 386 } 387 #endif 388