1 /*
2  * Copyright 2010 Freescale Semiconductor, Inc.
3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4  *          Timur Tabi <timur@freescale.com>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License as published by the Free
8  * Software Foundation; either version 2 of the License, or (at your option)
9  * any later version.
10  */
11 
12 #include <common.h>
13 #include <command.h>
14 #include <pci.h>
15 #include <asm/processor.h>
16 #include <asm/mmu.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_pci.h>
20 #include <asm/fsl_ddr_sdram.h>
21 #include <asm/fsl_serdes.h>
22 #include <asm/io.h>
23 #include <libfdt.h>
24 #include <fdt_support.h>
25 #include <tsec.h>
26 #include <asm/fsl_law.h>
27 #include <asm/mp.h>
28 #include <netdev.h>
29 #include <i2c.h>
30 
31 #include "../common/ngpixis.h"
32 
33 DECLARE_GLOBAL_DATA_PTR;
34 
35 int board_early_init_f(void)
36 {
37 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
38 
39 	/* Set pmuxcr to allow both i2c1 and i2c2 */
40 	setbits_be32(&gur->pmuxcr, 0x1000);
41 
42 	/* Read back the register to synchronize the write. */
43 	in_be32(&gur->pmuxcr);
44 
45 	/* Set the pin muxing to enable ETSEC2. */
46 	clrbits_be32(&gur->pmuxcr2, 0x001F8000);
47 
48 	return 0;
49 }
50 
51 int checkboard(void)
52 {
53 	u8 sw;
54 
55 	puts("Board: P1022DS ");
56 
57 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
58 		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
59 
60 	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
61 
62 	switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
63 	case 0:
64 		printf ("vBank: %u\n", ((sw & 0x30) >> 4));
65 		break;
66 	case 1:
67 		printf ("NAND\n");
68 		break;
69 	case 2:
70 	case 3:
71 		puts ("Promjet\n");
72 		break;
73 	}
74 
75 	return 0;
76 }
77 
78 phys_size_t initdram(int board_type)
79 {
80 	phys_size_t dram_size = 0;
81 
82 	puts("Initializing....\n");
83 
84 	dram_size = fsl_ddr_sdram();
85 	dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
86 
87 	puts("    DDR: ");
88 	return dram_size;
89 }
90 
91 #define CONFIG_TFP410_I2C_ADDR	0x38
92 
93 int misc_init_r(void)
94 {
95 	u8 temp;
96 
97 	/*  Enable the TFP410 Encoder */
98 
99 	temp = 0xBF;
100 	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
101 		return -1;
102 
103 	/* Verify if enabled */
104 	temp = 0;
105 	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
106 		return -1;
107 
108 	debug("DVI Encoder Read: 0x%02x\n", temp);
109 
110 	temp = 0x10;
111 	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
112 		return -1;
113 
114 	/* Verify if enabled */
115 	temp = 0;
116 	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
117 		return -1;
118 
119 	debug("DVI Encoder Read: 0x%02x\n",temp);
120 
121 	return 0;
122 }
123 
124 /*
125  * A list of PCI and SATA slots
126  */
127 enum slot_id {
128 	SLOT_PCIE1 = 1,
129 	SLOT_PCIE2,
130 	SLOT_PCIE3,
131 	SLOT_PCIE4,
132 	SLOT_PCIE5,
133 	SLOT_SATA1,
134 	SLOT_SATA2
135 };
136 
137 /*
138  * This array maps the slot identifiers to their names on the P1022DS board.
139  */
140 static const char *slot_names[] = {
141 	[SLOT_PCIE1] = "Slot 1",
142 	[SLOT_PCIE2] = "Slot 2",
143 	[SLOT_PCIE3] = "Slot 3",
144 	[SLOT_PCIE4] = "Slot 4",
145 	[SLOT_PCIE5] = "Mini-PCIe",
146 	[SLOT_SATA1] = "SATA 1",
147 	[SLOT_SATA2] = "SATA 2",
148 };
149 
150 /*
151  * This array maps a given SERDES configuration and SERDES device to the PCI or
152  * SATA slot that it connects to.  This mapping is hard-coded in the FPGA.
153  */
154 static u8 serdes_dev_slot[][SATA2 + 1] = {
155 	[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
156 	[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
157 	[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
158 		   [PCIE2] = SLOT_PCIE5 },
159 	[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
160 		   [PCIE2] = SLOT_PCIE3,
161 		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
162 	[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
163 		   [PCIE2] = SLOT_PCIE3 },
164 	[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
165 		   [PCIE2] = SLOT_PCIE3,
166 		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
167 	[0x1c] = { [PCIE1] = SLOT_PCIE1,
168 		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
169 	[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
170 	[0x1f] = { [PCIE1] = SLOT_PCIE1 },
171 };
172 
173 
174 /*
175  * Returns the name of the slot to which the PCIe or SATA controller is
176  * connected
177  */
178 const char *serdes_slot_name(enum srds_prtcl device)
179 {
180 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
181 	u32 pordevsr = in_be32(&gur->pordevsr);
182 	unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
183 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
184 	enum slot_id slot = serdes_dev_slot[srds_cfg][device];
185 	const char *name = slot_names[slot];
186 
187 	if (name)
188 		return name;
189 	else
190 		return "Nothing";
191 }
192 
193 static void configure_pcie(struct fsl_pci_info *info,
194 			   struct pci_controller *hose,
195 			   const char *connected)
196 {
197 	static int bus_number = 0;
198 	int is_endpoint;
199 
200 	set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
201 	set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
202 	is_endpoint = fsl_setup_hose(hose, info->regs);
203 	printf("    PCIE%u connected to %s as %s (base addr %lx)\n",
204 	       info->pci_num, connected,
205 	       is_endpoint ? "Endpoint" : "Root Complex", info->regs);
206 	bus_number = fsl_pci_init_port(info, hose, bus_number);
207 }
208 
209 #ifdef CONFIG_PCIE1
210 static struct pci_controller pcie1_hose;
211 #endif
212 
213 #ifdef CONFIG_PCIE2
214 static struct pci_controller pcie2_hose;
215 #endif
216 
217 #ifdef CONFIG_PCIE3
218 static struct pci_controller pcie3_hose;
219 #endif
220 
221 #ifdef CONFIG_PCI
222 void pci_init_board(void)
223 {
224 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
225 	struct fsl_pci_info pci_info;
226 	u32 devdisr = in_be32(&gur->devdisr);
227 
228 #ifdef CONFIG_PCIE1
229 	if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
230 		SET_STD_PCIE_INFO(pci_info, 1);
231 		configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
232 	} else {
233 		printf("    PCIE1: disabled\n");
234 	}
235 #else
236 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
237 #endif
238 
239 #ifdef CONFIG_PCIE2
240 	if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
241 		SET_STD_PCIE_INFO(pci_info, 2);
242 		configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
243 	} else {
244 		printf("    PCIE2: disabled\n");
245 	}
246 #else
247 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
248 #endif
249 
250 #ifdef CONFIG_PCIE3
251 	if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
252 		SET_STD_PCIE_INFO(pci_info, 3);
253 		configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
254 	} else {
255 		printf("    PCIE3: disabled\n");
256 	}
257 #else
258 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
259 #endif
260 }
261 #endif
262 
263 int board_early_init_r(void)
264 {
265 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
266 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
267 
268 	/*
269 	 * Remap Boot flash + PROMJET region to caching-inhibited
270 	 * so that flash can be erased properly.
271 	 */
272 
273 	/* Flush d-cache and invalidate i-cache of any FLASH data */
274 	flush_dcache();
275 	invalidate_icache();
276 
277 	/* invalidate existing TLB entry for flash + promjet */
278 	disable_tlb(flash_esel);
279 
280 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
281 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
282 			0, flash_esel, BOOKE_PAGESZ_256M, 1);
283 
284 	return 0;
285 }
286 
287 /*
288  * Initialize on-board and/or PCI Ethernet devices
289  *
290  * Returns:
291  *      <0, error
292  *       0, no ethernet devices found
293  *      >0, number of ethernet devices initialized
294  */
295 int board_eth_init(bd_t *bis)
296 {
297 	struct tsec_info_struct tsec_info[2];
298 	unsigned int num = 0;
299 
300 #ifdef CONFIG_TSEC1
301 	SET_STD_TSEC_INFO(tsec_info[num], 1);
302 	num++;
303 #endif
304 #ifdef CONFIG_TSEC2
305 	SET_STD_TSEC_INFO(tsec_info[num], 2);
306 	num++;
307 #endif
308 
309 	return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
310 }
311 
312 #ifdef CONFIG_OF_BOARD_SETUP
313 void ft_board_setup(void *blob, bd_t *bd)
314 {
315 	phys_addr_t base;
316 	phys_size_t size;
317 
318 	ft_cpu_setup(blob, bd);
319 
320 	base = getenv_bootm_low();
321 	size = getenv_bootm_size();
322 
323 	fdt_fixup_memory(blob, (u64)base, (u64)size);
324 
325 	FT_FSL_PCI_SETUP;
326 
327 #ifdef CONFIG_FSL_SGMII_RISER
328 	fsl_sgmii_riser_fdt_fixup(blob);
329 #endif
330 }
331 #endif
332 
333 #ifdef CONFIG_MP
334 void board_lmb_reserve(struct lmb *lmb)
335 {
336 	cpu_mp_lmb_reserve(lmb);
337 }
338 #endif
339