1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 */ 11 12 #include <common.h> 13 #include <command.h> 14 #include <pci.h> 15 #include <asm/processor.h> 16 #include <asm/mmu.h> 17 #include <asm/cache.h> 18 #include <asm/immap_85xx.h> 19 #include <asm/fsl_pci.h> 20 #include <asm/fsl_ddr_sdram.h> 21 #include <asm/fsl_serdes.h> 22 #include <asm/io.h> 23 #include <libfdt.h> 24 #include <fdt_support.h> 25 #include <fsl_mdio.h> 26 #include <tsec.h> 27 #include <asm/fsl_law.h> 28 #include <netdev.h> 29 #include <i2c.h> 30 #include <hwconfig.h> 31 32 #include "../common/ngpixis.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 int board_early_init_f(void) 37 { 38 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 39 40 /* Set pmuxcr to allow both i2c1 and i2c2 */ 41 setbits_be32(&gur->pmuxcr, 0x1000); 42 43 /* Read back the register to synchronize the write. */ 44 in_be32(&gur->pmuxcr); 45 46 /* Set the pin muxing to enable ETSEC2. */ 47 clrbits_be32(&gur->pmuxcr2, 0x001F8000); 48 49 /* Enable the SPI */ 50 clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); 51 52 return 0; 53 } 54 55 int checkboard(void) 56 { 57 u8 sw; 58 59 puts("Board: P1022DS "); 60 #ifdef CONFIG_PHYS_64BIT 61 puts("(36-bit addrmap) "); 62 #endif 63 64 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 65 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 66 67 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 68 69 switch ((sw & PIXIS_LBMAP_MASK) >> 6) { 70 case 0: 71 printf ("vBank: %u\n", ((sw & 0x30) >> 4)); 72 break; 73 case 1: 74 printf ("NAND\n"); 75 break; 76 case 2: 77 case 3: 78 puts ("Promjet\n"); 79 break; 80 } 81 82 return 0; 83 } 84 85 #define CONFIG_TFP410_I2C_ADDR 0x38 86 87 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ 88 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c 89 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03 90 91 /* Route the I2C1 pins to the SSI port instead. */ 92 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08 93 94 /* Choose the 12.288Mhz codec reference clock */ 95 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02 96 97 /* Choose the 11.2896Mhz codec reference clock */ 98 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 99 100 /* Connect to USB2 */ 101 #define CONFIG_PIXIS_BRDCFG0_USB2 0x10 102 /* Connect to TFM bus */ 103 #define CONFIG_PIXIS_BRDCFG1_TDM 0x0c 104 /* Connect to SPI */ 105 #define CONFIG_PIXIS_BRDCFG0_SPI 0x80 106 107 int misc_init_r(void) 108 { 109 u8 temp; 110 const char *audclk; 111 size_t arglen; 112 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 113 114 /* For DVI, enable the TFP410 Encoder. */ 115 116 temp = 0xBF; 117 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) 118 return -1; 119 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) 120 return -1; 121 debug("DVI Encoder Read: 0x%02x\n", temp); 122 123 temp = 0x10; 124 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) 125 return -1; 126 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) 127 return -1; 128 debug("DVI Encoder Read: 0x%02x\n",temp); 129 130 /* Enable the USB2 in PMUXCR2 and FGPA */ 131 if (hwconfig("usb2")) { 132 clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK, 133 MPC85xx_PMUXCR2_USB); 134 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2); 135 } 136 137 /* tdm and audio can not enable simultaneous*/ 138 if (hwconfig("tdm") && hwconfig("audclk")){ 139 printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n"); 140 return -1; 141 } 142 143 /* Enable the TDM in PMUXCR and FGPA */ 144 if (hwconfig("tdm")) { 145 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK, 146 MPC85xx_PMUXCR_TDM); 147 setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM); 148 /* TDM need some configration option by SPI */ 149 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK, 150 MPC85xx_PMUXCR_SPI); 151 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI); 152 } 153 154 /* 155 * Enable the reference clock for the WM8776 codec, and route the MUX 156 * pins for SSI. The default is the 12.288 MHz clock 157 */ 158 159 if (hwconfig("audclk")) { 160 temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | 161 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); 162 temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; 163 164 audclk = hwconfig_arg("audclk", &arglen); 165 /* Check the first two chars only */ 166 if (audclk && (strncmp(audclk, "11", 2) == 0)) 167 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; 168 else 169 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; 170 setbits_8(&pixis->brdcfg1, temp); 171 } 172 173 return 0; 174 } 175 176 /* 177 * A list of PCI and SATA slots 178 */ 179 enum slot_id { 180 SLOT_PCIE1 = 1, 181 SLOT_PCIE2, 182 SLOT_PCIE3, 183 SLOT_PCIE4, 184 SLOT_PCIE5, 185 SLOT_SATA1, 186 SLOT_SATA2 187 }; 188 189 /* 190 * This array maps the slot identifiers to their names on the P1022DS board. 191 */ 192 static const char *slot_names[] = { 193 [SLOT_PCIE1] = "Slot 1", 194 [SLOT_PCIE2] = "Slot 2", 195 [SLOT_PCIE3] = "Slot 3", 196 [SLOT_PCIE4] = "Slot 4", 197 [SLOT_PCIE5] = "Mini-PCIe", 198 [SLOT_SATA1] = "SATA 1", 199 [SLOT_SATA2] = "SATA 2", 200 }; 201 202 /* 203 * This array maps a given SERDES configuration and SERDES device to the PCI or 204 * SATA slot that it connects to. This mapping is hard-coded in the FPGA. 205 */ 206 static u8 serdes_dev_slot[][SATA2 + 1] = { 207 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, 208 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 209 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, 210 [PCIE2] = SLOT_PCIE5 }, 211 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 212 [PCIE2] = SLOT_PCIE3, 213 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 214 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 215 [PCIE2] = SLOT_PCIE3 }, 216 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, 217 [PCIE2] = SLOT_PCIE3, 218 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 219 [0x1c] = { [PCIE1] = SLOT_PCIE1, 220 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 221 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, 222 [0x1f] = { [PCIE1] = SLOT_PCIE1 }, 223 }; 224 225 226 /* 227 * Returns the name of the slot to which the PCIe or SATA controller is 228 * connected 229 */ 230 const char *board_serdes_name(enum srds_prtcl device) 231 { 232 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 233 u32 pordevsr = in_be32(&gur->pordevsr); 234 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 235 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 236 enum slot_id slot = serdes_dev_slot[srds_cfg][device]; 237 const char *name = slot_names[slot]; 238 239 if (name) 240 return name; 241 else 242 return "Nothing"; 243 } 244 245 #ifdef CONFIG_PCI 246 void pci_init_board(void) 247 { 248 fsl_pcie_init_board(0); 249 } 250 #endif 251 252 int board_early_init_r(void) 253 { 254 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 255 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 256 257 /* 258 * Remap Boot flash + PROMJET region to caching-inhibited 259 * so that flash can be erased properly. 260 */ 261 262 /* Flush d-cache and invalidate i-cache of any FLASH data */ 263 flush_dcache(); 264 invalidate_icache(); 265 266 /* invalidate existing TLB entry for flash + promjet */ 267 disable_tlb(flash_esel); 268 269 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 270 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 271 0, flash_esel, BOOKE_PAGESZ_256M, 1); 272 273 return 0; 274 } 275 276 /* 277 * Initialize on-board and/or PCI Ethernet devices 278 * 279 * Returns: 280 * <0, error 281 * 0, no ethernet devices found 282 * >0, number of ethernet devices initialized 283 */ 284 int board_eth_init(bd_t *bis) 285 { 286 struct fsl_pq_mdio_info mdio_info; 287 struct tsec_info_struct tsec_info[2]; 288 unsigned int num = 0; 289 290 #ifdef CONFIG_TSEC1 291 SET_STD_TSEC_INFO(tsec_info[num], 1); 292 num++; 293 #endif 294 #ifdef CONFIG_TSEC2 295 SET_STD_TSEC_INFO(tsec_info[num], 2); 296 num++; 297 #endif 298 299 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 300 mdio_info.name = DEFAULT_MII_NAME; 301 fsl_pq_mdio_init(bis, &mdio_info); 302 303 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); 304 } 305 306 #ifdef CONFIG_OF_BOARD_SETUP 307 /** 308 * ft_codec_setup - fix up the clock-frequency property of the codec node 309 * 310 * Update the clock-frequency property based on the value of the 'audclk' 311 * hwconfig option. If audclk is not specified, then don't write anything 312 * to the device tree, because it means that the codec clock is disabled. 313 */ 314 static void ft_codec_setup(void *blob, const char *compatible) 315 { 316 const char *audclk; 317 size_t arglen; 318 u32 freq; 319 320 audclk = hwconfig_arg("audclk", &arglen); 321 if (audclk) { 322 if (strncmp(audclk, "11", 2) == 0) 323 freq = 11289600; 324 else 325 freq = 12288000; 326 327 do_fixup_by_compat_u32(blob, compatible, "clock-frequency", 328 freq, 1); 329 } 330 } 331 332 void ft_board_setup(void *blob, bd_t *bd) 333 { 334 phys_addr_t base; 335 phys_size_t size; 336 337 ft_cpu_setup(blob, bd); 338 339 base = getenv_bootm_low(); 340 size = getenv_bootm_size(); 341 342 fdt_fixup_memory(blob, (u64)base, (u64)size); 343 344 FT_FSL_PCI_SETUP; 345 346 #ifdef CONFIG_FSL_SGMII_RISER 347 fsl_sgmii_riser_fdt_fixup(blob); 348 #endif 349 350 /* Update the WM8776 node's clock frequency property */ 351 ft_codec_setup(blob, "wlf,wm8776"); 352 } 353 #endif 354