1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2d5e01e49STimur Tabi /*
3aa8d3fb8STimur Tabi * Copyright 2010-2011 Freescale Semiconductor, Inc.
4d5e01e49STimur Tabi * Authors: Timur Tabi <timur@freescale.com>
5d5e01e49STimur Tabi *
6d5e01e49STimur Tabi * FSL DIU Framebuffer driver
7d5e01e49STimur Tabi */
8d5e01e49STimur Tabi
9d5e01e49STimur Tabi #include <common.h>
10d5e01e49STimur Tabi #include <command.h>
11ba8e76bdSTimur Tabi #include <linux/ctype.h>
12d5e01e49STimur Tabi #include <asm/io.h>
13d5e01e49STimur Tabi #include <stdio_dev.h>
14d5e01e49STimur Tabi #include <video_fb.h>
15d5e01e49STimur Tabi #include "../common/ngpixis.h"
16d5e01e49STimur Tabi #include <fsl_diu_fb.h>
17d5e01e49STimur Tabi
1855b05237STimur Tabi /* The CTL register is called 'csr' in the ngpixis_t structure */
1955b05237STimur Tabi #define PX_CTL_ALTACC 0x80
2055b05237STimur Tabi
2155b05237STimur Tabi #define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
2255b05237STimur Tabi #define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
2355b05237STimur Tabi #define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
24d5e01e49STimur Tabi #define PX_BRDCFG0_ELBC_DIU 0x02
25d5e01e49STimur Tabi
26d5e01e49STimur Tabi #define PX_BRDCFG1_DVIEN 0x80
27d5e01e49STimur Tabi #define PX_BRDCFG1_DFPEN 0x40
28d5e01e49STimur Tabi #define PX_BRDCFG1_BACKLIGHT 0x20
29d5e01e49STimur Tabi
3055b05237STimur Tabi #define PMUXCR_ELBCDIU_MASK 0xc0000000
3155b05237STimur Tabi #define PMUXCR_ELBCDIU_NOR16 0x80000000
32fdb9482bSTimur Tabi #define PMUXCR_ELBCDIU_DIU 0x40000000
3355b05237STimur Tabi
34d5e01e49STimur Tabi /*
35d5e01e49STimur Tabi * DIU Area Descriptor
36d5e01e49STimur Tabi *
37d5e01e49STimur Tabi * Note that we need to byte-swap the value before it's written to the AD
38d5e01e49STimur Tabi * register. So even though the registers don't look like they're in the same
39d5e01e49STimur Tabi * bit positions as they are on the MPC8610, the same value is written to the
40d5e01e49STimur Tabi * AD register on the MPC8610 and on the P1022.
41d5e01e49STimur Tabi */
42d5e01e49STimur Tabi #define AD_BYTE_F 0x10000000
43d5e01e49STimur Tabi #define AD_ALPHA_C_SHIFT 25
44d5e01e49STimur Tabi #define AD_BLUE_C_SHIFT 23
45d5e01e49STimur Tabi #define AD_GREEN_C_SHIFT 21
46d5e01e49STimur Tabi #define AD_RED_C_SHIFT 19
47d5e01e49STimur Tabi #define AD_PIXEL_S_SHIFT 16
48d5e01e49STimur Tabi #define AD_COMP_3_SHIFT 12
49d5e01e49STimur Tabi #define AD_COMP_2_SHIFT 8
50d5e01e49STimur Tabi #define AD_COMP_1_SHIFT 4
51d5e01e49STimur Tabi #define AD_COMP_0_SHIFT 0
52d5e01e49STimur Tabi
5355b05237STimur Tabi /*
5455b05237STimur Tabi * Variables used by the DIU/LBC switching code. It's safe to makes these
5555b05237STimur Tabi * global, because the DIU requires DDR, so we'll only run this code after
5655b05237STimur Tabi * relocation.
5755b05237STimur Tabi */
5855b05237STimur Tabi static u8 px_brdcfg0;
5955b05237STimur Tabi static u32 pmuxcr;
6055b05237STimur Tabi static void *lbc_lcs0_ba;
6155b05237STimur Tabi static void *lbc_lcs1_ba;
627a946961STimur Tabi static u32 old_br0, old_or0, old_br1, old_or1;
637a946961STimur Tabi static u32 new_br0, new_or0, new_br1, new_or1;
6455b05237STimur Tabi
diu_set_pixel_clock(unsigned int pixclock)65d5e01e49STimur Tabi void diu_set_pixel_clock(unsigned int pixclock)
66d5e01e49STimur Tabi {
67d5e01e49STimur Tabi ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
68d5e01e49STimur Tabi unsigned long speed_ccb, temp;
69d5e01e49STimur Tabi u32 pixval;
70d5e01e49STimur Tabi
71d5e01e49STimur Tabi speed_ccb = get_bus_freq(0);
72d5e01e49STimur Tabi temp = 1000000000 / pixclock;
73d5e01e49STimur Tabi temp *= 1000;
74d5e01e49STimur Tabi pixval = speed_ccb / temp;
751f09b44cSMarek Vasut debug("DIU pixval = %u\n", pixval);
76d5e01e49STimur Tabi
77d5e01e49STimur Tabi /* Modify PXCLK in GUTS CLKDVDR */
78d5e01e49STimur Tabi temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
79d5e01e49STimur Tabi out_be32(&gur->clkdvdr, temp); /* turn off clock */
80d5e01e49STimur Tabi out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
81d5e01e49STimur Tabi }
82d5e01e49STimur Tabi
platform_diu_init(unsigned int xres,unsigned int yres,const char * port)83ba8e76bdSTimur Tabi int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
84d5e01e49STimur Tabi {
85d5e01e49STimur Tabi ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
86ba8e76bdSTimur Tabi const char *name;
87d5e01e49STimur Tabi u32 pixel_format;
88d5e01e49STimur Tabi u8 temp;
897a946961STimur Tabi phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */
907a946961STimur Tabi
917a946961STimur Tabi /*
927a946961STimur Tabi * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
937a946961STimur Tabi * otherwise writes to these addresses won't actually appear on the
947a946961STimur Tabi * local bus, and so the PIXIS won't see them.
957a946961STimur Tabi *
967a946961STimur Tabi * In FCM mode, writes go to the NAND controller, which does not pass
977a946961STimur Tabi * them to the localbus directly. So we force BR0 and BR1 into GPCM
987a946961STimur Tabi * mode, since we don't care about what's behind the localbus any
997a946961STimur Tabi * more. However, we save those registers first, so that we can
1007a946961STimur Tabi * restore them when necessary.
1017a946961STimur Tabi */
1027a946961STimur Tabi new_br0 = old_br0 = get_lbc_br(0);
1037a946961STimur Tabi new_br1 = old_br1 = get_lbc_br(1);
1047a946961STimur Tabi new_or0 = old_or0 = get_lbc_or(0);
1057a946961STimur Tabi new_or1 = old_or1 = get_lbc_or(1);
1067a946961STimur Tabi
1077a946961STimur Tabi /*
1087a946961STimur Tabi * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
1097a946961STimur Tabi * force the values to simple 32KB GPCM windows with the most
1107a946961STimur Tabi * conservative timing.
1117a946961STimur Tabi */
1127a946961STimur Tabi if ((old_br0 & BR_MSEL) != BR_MS_GPCM) {
1137a946961STimur Tabi new_br0 = (get_lbc_br(0) & BR_BA) | BR_V;
1147a946961STimur Tabi new_or0 = OR_AM_32KB | 0xFF7;
1157a946961STimur Tabi set_lbc_br(0, new_br0);
1167a946961STimur Tabi set_lbc_or(0, new_or0);
1177a946961STimur Tabi }
1187a946961STimur Tabi if ((old_br1 & BR_MSEL) != BR_MS_GPCM) {
1197a946961STimur Tabi new_br1 = (get_lbc_br(1) & BR_BA) | BR_V;
1207a946961STimur Tabi new_or1 = OR_AM_32KB | 0xFF7;
1217a946961STimur Tabi set_lbc_br(1, new_br1);
1227a946961STimur Tabi set_lbc_or(1, new_or1);
1237a946961STimur Tabi }
1247a946961STimur Tabi
1257a946961STimur Tabi /*
1267a946961STimur Tabi * Determine the physical addresses for Chip Selects 0 and 1. The
1277a946961STimur Tabi * BR0/BR1 registers contain the truncated physical addresses for the
1287a946961STimur Tabi * chip selects, mapped via the localbus LAW. Since the BRx registers
1297a946961STimur Tabi * only contain the lower 32 bits of the address, we have to determine
1307a946961STimur Tabi * the upper 4 bits some other way. The proper way is to scan the LAW
1317a946961STimur Tabi * table looking for a matching localbus address. Instead, we cheat.
1327a946961STimur Tabi * We know that the upper bits are 0 for 32-bit addressing, or 0xF for
1337a946961STimur Tabi * 36-bit addressing.
1347a946961STimur Tabi */
1357a946961STimur Tabi #ifdef CONFIG_PHYS_64BIT
1367a946961STimur Tabi phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA);
1377a946961STimur Tabi phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA);
1387a946961STimur Tabi #else
1397a946961STimur Tabi phys0 = old_br0 & old_or0 & BR_BA;
1407a946961STimur Tabi phys1 = old_br1 & old_or1 & BR_BA;
1417a946961STimur Tabi #endif
142d5e01e49STimur Tabi
14355b05237STimur Tabi /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
1447a946961STimur Tabi lbc_lcs0_ba = map_physmem(phys0, 1, 0);
1457a946961STimur Tabi lbc_lcs1_ba = map_physmem(phys1, 1, 0);
14655b05237STimur Tabi
147d5e01e49STimur Tabi pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
148d5e01e49STimur Tabi (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
149d5e01e49STimur Tabi (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
150d5e01e49STimur Tabi (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
151d5e01e49STimur Tabi (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
152d5e01e49STimur Tabi
153d5e01e49STimur Tabi temp = in_8(&pixis->brdcfg1);
154d5e01e49STimur Tabi
155ba8e76bdSTimur Tabi if (strncmp(port, "lvds", 4) == 0) {
156ba8e76bdSTimur Tabi /* Single link LVDS */
157ba8e76bdSTimur Tabi temp &= ~PX_BRDCFG1_DVIEN;
158ba8e76bdSTimur Tabi /*
159ba8e76bdSTimur Tabi * LVDS also needs backlight enabled, otherwise the display
160ba8e76bdSTimur Tabi * will be blank.
161ba8e76bdSTimur Tabi */
162ba8e76bdSTimur Tabi temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
163ba8e76bdSTimur Tabi name = "Single-Link LVDS";
164d5e01e49STimur Tabi } else { /* DVI */
165d5e01e49STimur Tabi /* Enable the DVI port, disable the DFP and the backlight */
166d5e01e49STimur Tabi temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
167d5e01e49STimur Tabi temp |= PX_BRDCFG1_DVIEN;
168ba8e76bdSTimur Tabi name = "DVI";
169d5e01e49STimur Tabi }
170d5e01e49STimur Tabi
171ba8e76bdSTimur Tabi printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
172d5e01e49STimur Tabi out_8(&pixis->brdcfg1, temp);
173d5e01e49STimur Tabi
174d5e01e49STimur Tabi /*
17555b05237STimur Tabi * Enable PIXIS indirect access mode. This is a hack that allows us to
17655b05237STimur Tabi * access PIXIS registers even when the LBC pins have been muxed to the
17755b05237STimur Tabi * DIU.
17855b05237STimur Tabi */
17955b05237STimur Tabi setbits_8(&pixis->csr, PX_CTL_ALTACC);
18055b05237STimur Tabi
18155b05237STimur Tabi /*
182d5e01e49STimur Tabi * Route the LAD pins to the DIU. This will disable access to the eLBC,
183d5e01e49STimur Tabi * which means we won't be able to read/write any NOR flash addresses!
184d5e01e49STimur Tabi */
18555b05237STimur Tabi out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
18655b05237STimur Tabi px_brdcfg0 = in_8(lbc_lcs1_ba);
18755b05237STimur Tabi out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
1887a946961STimur Tabi in_8(lbc_lcs1_ba);
189d5e01e49STimur Tabi
190fdb9482bSTimur Tabi /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
191fdb9482bSTimur Tabi clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
19255b05237STimur Tabi pmuxcr = in_be32(&gur->pmuxcr);
193d5e01e49STimur Tabi
1943b4a2263STimur Tabi return fsl_diu_init(xres, yres, pixel_format, 0);
195d5e01e49STimur Tabi }
19655b05237STimur Tabi
19755b05237STimur Tabi /*
19855b05237STimur Tabi * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
19955b05237STimur Tabi *
20055b05237STimur Tabi * On the Freescale P1022, the DIU video signal and the LBC address/data lines
20155b05237STimur Tabi * share the same pins, which means that when the DIU is active (e.g. the
20255b05237STimur Tabi * console is on the DVI display), NOR flash cannot be accessed. So we use the
20355b05237STimur Tabi * weak accessor feature of the CFI flash code to temporarily switch the pin
20455b05237STimur Tabi * mux from DIU to LBC whenever we want to read or write flash. This has a
20555b05237STimur Tabi * significant performance penalty, but it's the only way to make it work.
20655b05237STimur Tabi *
20755b05237STimur Tabi * There are two muxes: one on the chip, and one on the board. The chip mux
20855b05237STimur Tabi * controls whether the pins are used for the DIU or the LBC, and it is
20955b05237STimur Tabi * set via PMUXCR. The board mux controls whether those signals go to
21055b05237STimur Tabi * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
21155b05237STimur Tabi */
set_mux_to_lbc(void)21255b05237STimur Tabi static int set_mux_to_lbc(void)
21355b05237STimur Tabi {
21455b05237STimur Tabi ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
21555b05237STimur Tabi
21655b05237STimur Tabi /* Switch the muxes only if they're currently set to DIU mode */
217fdb9482bSTimur Tabi if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
21855b05237STimur Tabi PMUXCR_ELBCDIU_NOR16) {
21955b05237STimur Tabi /*
22055b05237STimur Tabi * In DIU mode, the PIXIS can only be accessed indirectly
22155b05237STimur Tabi * since we can't read/write the LBC directly.
22255b05237STimur Tabi */
22355b05237STimur Tabi /* Set the board mux to LBC. This will disable the display. */
22455b05237STimur Tabi out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
2257a946961STimur Tabi out_8(lbc_lcs1_ba, px_brdcfg0);
2267a946961STimur Tabi in_8(lbc_lcs1_ba);
22755b05237STimur Tabi
22855b05237STimur Tabi /* Disable indirect PIXIS mode */
22955b05237STimur Tabi out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
23055b05237STimur Tabi clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
23155b05237STimur Tabi
23255b05237STimur Tabi /* Set the chip mux to LBC mode, so that writes go to flash. */
23355b05237STimur Tabi out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
23455b05237STimur Tabi PMUXCR_ELBCDIU_NOR16);
23555b05237STimur Tabi in_be32(&gur->pmuxcr);
23655b05237STimur Tabi
2377a946961STimur Tabi /* Restore the BR0 and BR1 settings */
2387a946961STimur Tabi set_lbc_br(0, old_br0);
2397a946961STimur Tabi set_lbc_or(0, old_or0);
2407a946961STimur Tabi set_lbc_br(1, old_br1);
2417a946961STimur Tabi set_lbc_or(1, old_or1);
2427a946961STimur Tabi
24355b05237STimur Tabi return 1;
24455b05237STimur Tabi }
24555b05237STimur Tabi
24655b05237STimur Tabi return 0;
24755b05237STimur Tabi }
24855b05237STimur Tabi
24955b05237STimur Tabi /*
25055b05237STimur Tabi * set_mux_to_diu - re-enable the DIU muxing
25155b05237STimur Tabi *
25255b05237STimur Tabi * This function restores the chip and board muxing to point to the DIU.
25355b05237STimur Tabi */
set_mux_to_diu(void)25455b05237STimur Tabi static void set_mux_to_diu(void)
25555b05237STimur Tabi {
25655b05237STimur Tabi ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
25755b05237STimur Tabi
2587a946961STimur Tabi /* Set BR0 and BR1 to GPCM mode */
2597a946961STimur Tabi set_lbc_br(0, new_br0);
2607a946961STimur Tabi set_lbc_or(0, new_or0);
2617a946961STimur Tabi set_lbc_br(1, new_br1);
2627a946961STimur Tabi set_lbc_or(1, new_or1);
2637a946961STimur Tabi
26455b05237STimur Tabi /* Enable indirect PIXIS mode */
26555b05237STimur Tabi setbits_8(&pixis->csr, PX_CTL_ALTACC);
26655b05237STimur Tabi
26755b05237STimur Tabi /* Set the board mux to DIU. This will enable the display. */
26855b05237STimur Tabi out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
2697a946961STimur Tabi out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
27055b05237STimur Tabi in_8(lbc_lcs1_ba);
27155b05237STimur Tabi
27255b05237STimur Tabi /* Set the chip mux to DIU mode. */
27355b05237STimur Tabi out_be32(&gur->pmuxcr, pmuxcr);
27455b05237STimur Tabi in_be32(&gur->pmuxcr);
27555b05237STimur Tabi }
27655b05237STimur Tabi
277aa8d3fb8STimur Tabi /*
278aa8d3fb8STimur Tabi * pixis_read - board-specific function to read from the PIXIS
279aa8d3fb8STimur Tabi *
280aa8d3fb8STimur Tabi * This function overrides the generic pixis_read() function, so that it can
281aa8d3fb8STimur Tabi * use PIXIS indirect mode if necessary.
282aa8d3fb8STimur Tabi */
pixis_read(unsigned int reg)283aa8d3fb8STimur Tabi u8 pixis_read(unsigned int reg)
284aa8d3fb8STimur Tabi {
285aa8d3fb8STimur Tabi ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
286aa8d3fb8STimur Tabi
287aa8d3fb8STimur Tabi /* Use indirect mode if the mux is currently set to DIU mode */
288aa8d3fb8STimur Tabi if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
289aa8d3fb8STimur Tabi PMUXCR_ELBCDIU_NOR16) {
290aa8d3fb8STimur Tabi out_8(lbc_lcs0_ba, reg);
291aa8d3fb8STimur Tabi return in_8(lbc_lcs1_ba);
292aa8d3fb8STimur Tabi } else {
293aa8d3fb8STimur Tabi void *p = (void *)PIXIS_BASE;
294aa8d3fb8STimur Tabi
295aa8d3fb8STimur Tabi return in_8(p + reg);
296aa8d3fb8STimur Tabi }
297aa8d3fb8STimur Tabi }
298aa8d3fb8STimur Tabi
299aa8d3fb8STimur Tabi /*
300aa8d3fb8STimur Tabi * pixis_write - board-specific function to write to the PIXIS
301aa8d3fb8STimur Tabi *
302aa8d3fb8STimur Tabi * This function overrides the generic pixis_write() function, so that it can
303aa8d3fb8STimur Tabi * use PIXIS indirect mode if necessary.
304aa8d3fb8STimur Tabi */
pixis_write(unsigned int reg,u8 value)305aa8d3fb8STimur Tabi void pixis_write(unsigned int reg, u8 value)
306aa8d3fb8STimur Tabi {
307aa8d3fb8STimur Tabi ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
308aa8d3fb8STimur Tabi
309aa8d3fb8STimur Tabi /* Use indirect mode if the mux is currently set to DIU mode */
310aa8d3fb8STimur Tabi if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
311aa8d3fb8STimur Tabi PMUXCR_ELBCDIU_NOR16) {
312aa8d3fb8STimur Tabi out_8(lbc_lcs0_ba, reg);
313aa8d3fb8STimur Tabi out_8(lbc_lcs1_ba, value);
314aa8d3fb8STimur Tabi /* Do a read-back to ensure the write completed */
315aa8d3fb8STimur Tabi in_8(lbc_lcs1_ba);
316aa8d3fb8STimur Tabi } else {
317aa8d3fb8STimur Tabi void *p = (void *)PIXIS_BASE;
318aa8d3fb8STimur Tabi
319aa8d3fb8STimur Tabi out_8(p + reg, value);
320aa8d3fb8STimur Tabi }
321aa8d3fb8STimur Tabi }
322aa8d3fb8STimur Tabi
pixis_bank_reset(void)323aa8d3fb8STimur Tabi void pixis_bank_reset(void)
324aa8d3fb8STimur Tabi {
325aa8d3fb8STimur Tabi /*
326aa8d3fb8STimur Tabi * For some reason, a PIXIS bank reset does not work if the PIXIS is
327aa8d3fb8STimur Tabi * in indirect mode, so switch to direct mode first.
328aa8d3fb8STimur Tabi */
329aa8d3fb8STimur Tabi set_mux_to_lbc();
330aa8d3fb8STimur Tabi
331aa8d3fb8STimur Tabi out_8(&pixis->vctl, 0);
332aa8d3fb8STimur Tabi out_8(&pixis->vctl, 1);
333aa8d3fb8STimur Tabi
334aa8d3fb8STimur Tabi while (1);
335aa8d3fb8STimur Tabi }
336aa8d3fb8STimur Tabi
337aa8d3fb8STimur Tabi #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
338aa8d3fb8STimur Tabi
flash_write8(u8 value,void * addr)33955b05237STimur Tabi void flash_write8(u8 value, void *addr)
34055b05237STimur Tabi {
34155b05237STimur Tabi int sw = set_mux_to_lbc();
34255b05237STimur Tabi
34355b05237STimur Tabi __raw_writeb(value, addr);
344fdb9482bSTimur Tabi if (sw) {
345fdb9482bSTimur Tabi /*
346fdb9482bSTimur Tabi * To ensure the post-write is completed to eLBC, software must
347fdb9482bSTimur Tabi * perform a dummy read from one valid address from eLBC space
348fdb9482bSTimur Tabi * before changing the eLBC_DIU from NOR mode to DIU mode.
349fdb9482bSTimur Tabi * set_mux_to_diu() includes a sync that will ensure the
350fdb9482bSTimur Tabi * __raw_readb() completes before it switches the mux.
351fdb9482bSTimur Tabi */
352fdb9482bSTimur Tabi __raw_readb(addr);
35355b05237STimur Tabi set_mux_to_diu();
35455b05237STimur Tabi }
355fdb9482bSTimur Tabi }
35655b05237STimur Tabi
flash_write16(u16 value,void * addr)35755b05237STimur Tabi void flash_write16(u16 value, void *addr)
35855b05237STimur Tabi {
35955b05237STimur Tabi int sw = set_mux_to_lbc();
36055b05237STimur Tabi
36155b05237STimur Tabi __raw_writew(value, addr);
362fdb9482bSTimur Tabi if (sw) {
363fdb9482bSTimur Tabi /*
364fdb9482bSTimur Tabi * To ensure the post-write is completed to eLBC, software must
365fdb9482bSTimur Tabi * perform a dummy read from one valid address from eLBC space
366fdb9482bSTimur Tabi * before changing the eLBC_DIU from NOR mode to DIU mode.
367fdb9482bSTimur Tabi * set_mux_to_diu() includes a sync that will ensure the
368fdb9482bSTimur Tabi * __raw_readb() completes before it switches the mux.
369fdb9482bSTimur Tabi */
370fdb9482bSTimur Tabi __raw_readb(addr);
37155b05237STimur Tabi set_mux_to_diu();
37255b05237STimur Tabi }
373fdb9482bSTimur Tabi }
37455b05237STimur Tabi
flash_write32(u32 value,void * addr)37555b05237STimur Tabi void flash_write32(u32 value, void *addr)
37655b05237STimur Tabi {
37755b05237STimur Tabi int sw = set_mux_to_lbc();
37855b05237STimur Tabi
37955b05237STimur Tabi __raw_writel(value, addr);
380fdb9482bSTimur Tabi if (sw) {
381fdb9482bSTimur Tabi /*
382fdb9482bSTimur Tabi * To ensure the post-write is completed to eLBC, software must
383fdb9482bSTimur Tabi * perform a dummy read from one valid address from eLBC space
384fdb9482bSTimur Tabi * before changing the eLBC_DIU from NOR mode to DIU mode.
385fdb9482bSTimur Tabi * set_mux_to_diu() includes a sync that will ensure the
386fdb9482bSTimur Tabi * __raw_readb() completes before it switches the mux.
387fdb9482bSTimur Tabi */
388fdb9482bSTimur Tabi __raw_readb(addr);
38955b05237STimur Tabi set_mux_to_diu();
39055b05237STimur Tabi }
391fdb9482bSTimur Tabi }
39255b05237STimur Tabi
flash_write64(u64 value,void * addr)39355b05237STimur Tabi void flash_write64(u64 value, void *addr)
39455b05237STimur Tabi {
39555b05237STimur Tabi int sw = set_mux_to_lbc();
396fdb9482bSTimur Tabi uint32_t *p = addr;
39755b05237STimur Tabi
398fdb9482bSTimur Tabi /*
399fdb9482bSTimur Tabi * There is no __raw_writeq(), so do the write manually. We don't trust
400fdb9482bSTimur Tabi * the compiler, so we use inline assembly.
401fdb9482bSTimur Tabi */
402fdb9482bSTimur Tabi __asm__ __volatile__(
403fdb9482bSTimur Tabi "stw%U0%X0 %2,%0;\n"
404fdb9482bSTimur Tabi "stw%U1%X1 %3,%1;\n"
405fdb9482bSTimur Tabi : "=m" (*p), "=m" (*(p + 1))
406fdb9482bSTimur Tabi : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
407fdb9482bSTimur Tabi
408fdb9482bSTimur Tabi if (sw) {
409fdb9482bSTimur Tabi /*
410fdb9482bSTimur Tabi * To ensure the post-write is completed to eLBC, software must
411fdb9482bSTimur Tabi * perform a dummy read from one valid address from eLBC space
412fdb9482bSTimur Tabi * before changing the eLBC_DIU from NOR mode to DIU mode. We
413fdb9482bSTimur Tabi * read addr+4 because we just wrote to addr+4, so that's how we
414fdb9482bSTimur Tabi * maintain execution order. set_mux_to_diu() includes a sync
415fdb9482bSTimur Tabi * that will ensure the __raw_readb() completes before it
416fdb9482bSTimur Tabi * switches the mux.
417fdb9482bSTimur Tabi */
418fdb9482bSTimur Tabi __raw_readb(addr + 4);
41955b05237STimur Tabi set_mux_to_diu();
42055b05237STimur Tabi }
421fdb9482bSTimur Tabi }
42255b05237STimur Tabi
flash_read8(void * addr)42355b05237STimur Tabi u8 flash_read8(void *addr)
42455b05237STimur Tabi {
42555b05237STimur Tabi u8 ret;
42655b05237STimur Tabi
42755b05237STimur Tabi int sw = set_mux_to_lbc();
42855b05237STimur Tabi
42955b05237STimur Tabi ret = __raw_readb(addr);
43055b05237STimur Tabi if (sw)
43155b05237STimur Tabi set_mux_to_diu();
43255b05237STimur Tabi
43355b05237STimur Tabi return ret;
43455b05237STimur Tabi }
43555b05237STimur Tabi
flash_read16(void * addr)43655b05237STimur Tabi u16 flash_read16(void *addr)
43755b05237STimur Tabi {
43855b05237STimur Tabi u16 ret;
43955b05237STimur Tabi
44055b05237STimur Tabi int sw = set_mux_to_lbc();
44155b05237STimur Tabi
44255b05237STimur Tabi ret = __raw_readw(addr);
44355b05237STimur Tabi if (sw)
44455b05237STimur Tabi set_mux_to_diu();
44555b05237STimur Tabi
44655b05237STimur Tabi return ret;
44755b05237STimur Tabi }
44855b05237STimur Tabi
flash_read32(void * addr)44955b05237STimur Tabi u32 flash_read32(void *addr)
45055b05237STimur Tabi {
45155b05237STimur Tabi u32 ret;
45255b05237STimur Tabi
45355b05237STimur Tabi int sw = set_mux_to_lbc();
45455b05237STimur Tabi
45555b05237STimur Tabi ret = __raw_readl(addr);
45655b05237STimur Tabi if (sw)
45755b05237STimur Tabi set_mux_to_diu();
45855b05237STimur Tabi
45955b05237STimur Tabi return ret;
46055b05237STimur Tabi }
46155b05237STimur Tabi
flash_read64(void * addr)46255b05237STimur Tabi u64 flash_read64(void *addr)
46355b05237STimur Tabi {
46455b05237STimur Tabi u64 ret;
46555b05237STimur Tabi
46655b05237STimur Tabi int sw = set_mux_to_lbc();
46755b05237STimur Tabi
46855b05237STimur Tabi /* There is no __raw_readq(), so do the read manually */
46955b05237STimur Tabi ret = *(volatile u64 *)addr;
47055b05237STimur Tabi if (sw)
47155b05237STimur Tabi set_mux_to_diu();
47255b05237STimur Tabi
47355b05237STimur Tabi return ret;
47455b05237STimur Tabi }
47555b05237STimur Tabi
47655b05237STimur Tabi #endif
477