1 /* 2 * Copyright 2010 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 */ 11 12 #include <common.h> 13 14 #include <asm/fsl_ddr_sdram.h> 15 #include <asm/fsl_ddr_dimm_params.h> 16 17 typedef struct { 18 u32 datarate_mhz_low; 19 u32 datarate_mhz_high; 20 u32 n_ranks; 21 u32 clk_adjust; /* Range: 0-8 */ 22 u32 cpo; /* Range: 2-31 */ 23 u32 write_data_delay; /* Range: 0-6 */ 24 u32 force_2T; 25 } board_specific_parameters_t; 26 27 static const board_specific_parameters_t bsp[] = { 28 /* 29 * lo| hi| num| clk| cpo|wrdata|2T 30 * mhz| mhz|ranks|adjst| | delay| 31 */ 32 { 0, 333, 1, 5, 31, 3, 0}, 33 {334, 400, 1, 5, 31, 3, 0}, 34 {401, 549, 1, 5, 31, 3, 0}, 35 {550, 680, 1, 5, 31, 5, 0}, 36 {681, 850, 1, 5, 31, 5, 0}, 37 { 0, 333, 2, 5, 31, 3, 0}, 38 {334, 400, 2, 5, 31, 3, 0}, 39 {401, 549, 2, 5, 31, 3, 0}, 40 {550, 680, 2, 5, 31, 5, 0}, 41 {681, 850, 2, 5, 31, 5, 0}, 42 }; 43 44 void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, 45 unsigned int ctrl_num) 46 { 47 unsigned long ddr_freq; 48 unsigned int i; 49 50 /* set odt_rd_cfg and odt_wr_cfg. */ 51 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 52 popts->cs_local_opts[i].odt_rd_cfg = 0; 53 popts->cs_local_opts[i].odt_wr_cfg = 1; 54 } 55 56 /* 57 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 58 * freqency and n_banks specified in board_specific_parameters table. 59 */ 60 ddr_freq = get_ddr_freq(0) / 1000000; 61 for (i = 0; i < ARRAY_SIZE(bsp); i++) { 62 if (ddr_freq >= bsp[i].datarate_mhz_low && 63 ddr_freq <= bsp[i].datarate_mhz_high && 64 pdimm->n_ranks == bsp[i].n_ranks) { 65 popts->clk_adjust = bsp[i].clk_adjust; 66 popts->cpo_override = bsp[i].cpo; 67 popts->write_data_delay = bsp[i].write_data_delay; 68 popts->twoT_en = bsp[i].force_2T; 69 break; 70 } 71 } 72 73 popts->half_strength_driver_enable = 1; 74 75 /* Per AN4039, enable ZQ calibration. */ 76 popts->zq_en = 1; 77 78 /* 79 * For wake-up on ARP, we need auto self refresh enabled 80 */ 81 popts->auto_self_refresh_en = 1; 82 popts->sr_it = 0xb; 83 } 84