1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2010 Freescale Semiconductor, Inc. 4 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 5 * Timur Tabi <timur@freescale.com> 6 */ 7 8 #include <common.h> 9 10 #include <fsl_ddr_sdram.h> 11 #include <fsl_ddr_dimm_params.h> 12 13 struct board_specific_parameters { 14 u32 n_ranks; 15 u32 datarate_mhz_high; 16 u32 clk_adjust; /* Range: 0-8 */ 17 u32 cpo; /* Range: 2-31 */ 18 u32 write_data_delay; /* Range: 0-6 */ 19 u32 force_2t; 20 }; 21 22 /* 23 * This table contains all valid speeds we want to override with board 24 * specific parameters. datarate_mhz_high values need to be in ascending order 25 * for each n_ranks group. 26 */ 27 static const struct board_specific_parameters dimm0[] = { 28 /* 29 * memory controller 0 30 * num| hi| clk| cpo|wrdata|2T 31 * ranks| mhz|adjst| | delay| 32 */ 33 {1, 549, 5, 31, 3, 0}, 34 {1, 850, 5, 31, 5, 0}, 35 {2, 549, 5, 31, 3, 0}, 36 {2, 850, 5, 31, 5, 0}, 37 {} 38 }; 39 40 void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, 41 unsigned int ctrl_num) 42 { 43 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 44 unsigned long ddr_freq; 45 unsigned int i; 46 47 48 if (ctrl_num) { 49 printf("Wrong parameter for controller number %d", ctrl_num); 50 return; 51 } 52 if (!pdimm->n_ranks) 53 return; 54 55 /* set odt_rd_cfg and odt_wr_cfg. */ 56 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 57 popts->cs_local_opts[i].odt_rd_cfg = 0; 58 popts->cs_local_opts[i].odt_wr_cfg = 1; 59 } 60 61 pbsp = dimm0; 62 /* 63 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 64 * freqency and n_banks specified in board_specific_parameters table. 65 */ 66 ddr_freq = get_ddr_freq(0) / 1000000; 67 while (pbsp->datarate_mhz_high) { 68 if (pbsp->n_ranks == pdimm->n_ranks) { 69 if (ddr_freq <= pbsp->datarate_mhz_high) { 70 popts->clk_adjust = pbsp->clk_adjust; 71 popts->cpo_override = pbsp->cpo; 72 popts->write_data_delay = 73 pbsp->write_data_delay; 74 popts->twot_en = pbsp->force_2t; 75 goto found; 76 } 77 pbsp_highest = pbsp; 78 } 79 pbsp++; 80 } 81 82 if (pbsp_highest) { 83 printf("Error: board specific timing not found " 84 "for data rate %lu MT/s!\n" 85 "Trying to use the highest speed (%u) parameters\n", 86 ddr_freq, pbsp_highest->datarate_mhz_high); 87 popts->clk_adjust = pbsp->clk_adjust; 88 popts->cpo_override = pbsp->cpo; 89 popts->write_data_delay = pbsp->write_data_delay; 90 popts->twot_en = pbsp->force_2t; 91 } else { 92 panic("DIMM is not supported by this board"); 93 } 94 95 found: 96 popts->half_strength_driver_enable = 1; 97 98 /* Per AN4039, enable ZQ calibration. */ 99 popts->zq_en = 1; 100 101 /* 102 * For wake-up on ARP, we need auto self refresh enabled 103 */ 104 popts->auto_self_refresh_en = 1; 105 popts->sr_it = 0xb; 106 } 107