1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/mmu.h> 8 9 struct fsl_e_tlb_entry tlb_table[] = { 10 /* TLB 0 - for temp stack in cache */ 11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 12 MAS3_SX|MAS3_SW|MAS3_SR, 0, 13 0, 0, BOOKE_PAGESZ_4K, 0), 14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 15 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 16 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 0, 0, BOOKE_PAGESZ_4K, 0), 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 19 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 20 MAS3_SX|MAS3_SW|MAS3_SR, 0, 21 0, 0, BOOKE_PAGESZ_4K, 0), 22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 23 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 24 MAS3_SX|MAS3_SW|MAS3_SR, 0, 25 0, 0, BOOKE_PAGESZ_4K, 0), 26 27 /* TLB 1 */ 28 /* *I*** - Covers boot page */ 29 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 30 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 31 0, 0, BOOKE_PAGESZ_4K, 1), 32 #ifdef CONFIG_SPL_NAND_BOOT 33 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 34 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 35 0, 10, BOOKE_PAGESZ_4K, 1), 36 #endif 37 38 /* *I*G* - CCSRBAR */ 39 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 40 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41 0, 1, BOOKE_PAGESZ_1M, 1), 42 43 #ifndef CONFIG_SPL_BUILD 44 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 45 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 46 0, 2, BOOKE_PAGESZ_16M, 1), 47 48 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, 49 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, 50 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 51 0, 3, BOOKE_PAGESZ_16M, 1), 52 53 #ifdef CONFIG_PCI 54 /* *I*G* - PCI */ 55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 56 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57 0, 4, BOOKE_PAGESZ_1G, 1), 58 59 /* *I*G* - PCI I/O */ 60 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 61 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62 0, 5, BOOKE_PAGESZ_256K, 1), 63 #endif 64 #endif 65 66 /* *I*G - Board CPLD */ 67 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 68 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 69 0, 6, BOOKE_PAGESZ_256K, 1), 70 71 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 73 0, 7, BOOKE_PAGESZ_1M, 1), 74 75 #if defined(CONFIG_SYS_RAMBOOT) || \ 76 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) 77 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 78 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 79 0, 8, BOOKE_PAGESZ_1G, 1), 80 #endif 81 82 #ifdef CONFIG_SYS_INIT_L2_ADDR 83 /* *I*G - L2SRAM */ 84 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 85 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 86 0, 11, BOOKE_PAGESZ_256K, 1) 87 #endif 88 }; 89 90 int num_tlb_entries = ARRAY_SIZE(tlb_table); 91