1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/mmu.h> 9 10 struct fsl_e_tlb_entry tlb_table[] = { 11 /* TLB 0 - for temp stack in cache */ 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 13 MAS3_SX|MAS3_SW|MAS3_SR, 0, 14 0, 0, BOOKE_PAGESZ_4K, 0), 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 16 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17 MAS3_SX|MAS3_SW|MAS3_SR, 0, 18 0, 0, BOOKE_PAGESZ_4K, 0), 19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 20 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21 MAS3_SX|MAS3_SW|MAS3_SR, 0, 22 0, 0, BOOKE_PAGESZ_4K, 0), 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 24 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 28 /* TLB 1 */ 29 /* *I*** - Covers boot page */ 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 32 0, 0, BOOKE_PAGESZ_4K, 1), 33 #ifdef CONFIG_SPL_NAND_BOOT 34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36 0, 10, BOOKE_PAGESZ_4K, 1), 37 #endif 38 39 /* *I*G* - CCSRBAR */ 40 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 41 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 42 0, 1, BOOKE_PAGESZ_1M, 1), 43 44 #ifndef CONFIG_SPL_BUILD 45 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 46 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 47 0, 2, BOOKE_PAGESZ_16M, 1), 48 49 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, 50 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, 51 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 52 0, 3, BOOKE_PAGESZ_16M, 1), 53 54 #ifdef CONFIG_PCI 55 /* *I*G* - PCI */ 56 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 57 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 58 0, 4, BOOKE_PAGESZ_1G, 1), 59 60 /* *I*G* - PCI I/O */ 61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 62 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63 0, 5, BOOKE_PAGESZ_256K, 1), 64 #endif 65 #endif 66 67 /* *I*G - Board CPLD */ 68 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 69 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 70 0, 6, BOOKE_PAGESZ_256K, 1), 71 72 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 74 0, 7, BOOKE_PAGESZ_1M, 1), 75 76 #if defined(CONFIG_SYS_RAMBOOT) || \ 77 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) 78 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 79 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 80 0, 8, BOOKE_PAGESZ_1G, 1), 81 #endif 82 83 #ifdef CONFIG_SYS_INIT_L2_ADDR 84 /* *I*G - L2SRAM */ 85 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 87 0, 11, BOOKE_PAGESZ_256K, 1) 88 #endif 89 }; 90 91 int num_tlb_entries = ARRAY_SIZE(tlb_table); 92