1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 249249e13SPoonam Aggrwal /* 349249e13SPoonam Aggrwal * Copyright 2010-2011 Freescale Semiconductor, Inc. 449249e13SPoonam Aggrwal */ 549249e13SPoonam Aggrwal 649249e13SPoonam Aggrwal #include <common.h> 749249e13SPoonam Aggrwal #include <asm/mmu.h> 849249e13SPoonam Aggrwal 949249e13SPoonam Aggrwal struct fsl_e_tlb_entry tlb_table[] = { 1049249e13SPoonam Aggrwal /* TLB 0 - for temp stack in cache */ 1149249e13SPoonam Aggrwal SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 1249249e13SPoonam Aggrwal MAS3_SX|MAS3_SW|MAS3_SR, 0, 1349249e13SPoonam Aggrwal 0, 0, BOOKE_PAGESZ_4K, 0), 1449249e13SPoonam Aggrwal SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 1549249e13SPoonam Aggrwal CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 1649249e13SPoonam Aggrwal MAS3_SX|MAS3_SW|MAS3_SR, 0, 1749249e13SPoonam Aggrwal 0, 0, BOOKE_PAGESZ_4K, 0), 1849249e13SPoonam Aggrwal SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 1949249e13SPoonam Aggrwal CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 2049249e13SPoonam Aggrwal MAS3_SX|MAS3_SW|MAS3_SR, 0, 2149249e13SPoonam Aggrwal 0, 0, BOOKE_PAGESZ_4K, 0), 2249249e13SPoonam Aggrwal SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 2349249e13SPoonam Aggrwal CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 2449249e13SPoonam Aggrwal MAS3_SX|MAS3_SW|MAS3_SR, 0, 2549249e13SPoonam Aggrwal 0, 0, BOOKE_PAGESZ_4K, 0), 2649249e13SPoonam Aggrwal 2749249e13SPoonam Aggrwal /* TLB 1 */ 2849249e13SPoonam Aggrwal /* *I*** - Covers boot page */ 29f64bd7c0SPrabhakar Kushwaha SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 30f64bd7c0SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 31f64bd7c0SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 1), 32fbe76ae4SPrabhakar Kushwaha #ifdef CONFIG_SPL_NAND_BOOT 330fa934d2SPrabhakar Kushwaha SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 3449249e13SPoonam Aggrwal MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 35f64bd7c0SPrabhakar Kushwaha 0, 10, BOOKE_PAGESZ_4K, 1), 36f64bd7c0SPrabhakar Kushwaha #endif 3749249e13SPoonam Aggrwal 3849249e13SPoonam Aggrwal /* *I*G* - CCSRBAR */ 3949249e13SPoonam Aggrwal SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 4049249e13SPoonam Aggrwal MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 4149249e13SPoonam Aggrwal 0, 1, BOOKE_PAGESZ_1M, 1), 4249249e13SPoonam Aggrwal 430fa934d2SPrabhakar Kushwaha #ifndef CONFIG_SPL_BUILD 4449249e13SPoonam Aggrwal SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 4549249e13SPoonam Aggrwal MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 4649249e13SPoonam Aggrwal 0, 2, BOOKE_PAGESZ_16M, 1), 4749249e13SPoonam Aggrwal 4849249e13SPoonam Aggrwal SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, 4949249e13SPoonam Aggrwal CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, 5049249e13SPoonam Aggrwal MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 5149249e13SPoonam Aggrwal 0, 3, BOOKE_PAGESZ_16M, 1), 5249249e13SPoonam Aggrwal 53505c293fSPrabhakar Kushwaha #ifdef CONFIG_PCI 5449249e13SPoonam Aggrwal /* *I*G* - PCI */ 5549249e13SPoonam Aggrwal SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 5649249e13SPoonam Aggrwal MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 5749249e13SPoonam Aggrwal 0, 4, BOOKE_PAGESZ_1G, 1), 5849249e13SPoonam Aggrwal 5949249e13SPoonam Aggrwal /* *I*G* - PCI I/O */ 6049249e13SPoonam Aggrwal SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 6149249e13SPoonam Aggrwal MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 6249249e13SPoonam Aggrwal 0, 5, BOOKE_PAGESZ_256K, 1), 6349249e13SPoonam Aggrwal #endif 6449249e13SPoonam Aggrwal #endif 6549249e13SPoonam Aggrwal 6649249e13SPoonam Aggrwal /* *I*G - Board CPLD */ 6749249e13SPoonam Aggrwal SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 6849249e13SPoonam Aggrwal MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 6949249e13SPoonam Aggrwal 0, 6, BOOKE_PAGESZ_256K, 1), 7049249e13SPoonam Aggrwal 7149249e13SPoonam Aggrwal SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 7249249e13SPoonam Aggrwal MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 7349249e13SPoonam Aggrwal 0, 7, BOOKE_PAGESZ_1M, 1), 7449249e13SPoonam Aggrwal 75c9e1f588SYing Zhang #if defined(CONFIG_SYS_RAMBOOT) || \ 76c9e1f588SYing Zhang (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) 7749249e13SPoonam Aggrwal SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 78316f0d0fSYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 79c9e1f588SYing Zhang 0, 8, BOOKE_PAGESZ_1G, 1), 80c9e1f588SYing Zhang #endif 81c9e1f588SYing Zhang 82c9e1f588SYing Zhang #ifdef CONFIG_SYS_INIT_L2_ADDR 83c9e1f588SYing Zhang /* *I*G - L2SRAM */ 84c9e1f588SYing Zhang SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 85c9e1f588SYing Zhang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 86c9e1f588SYing Zhang 0, 11, BOOKE_PAGESZ_256K, 1) 8749249e13SPoonam Aggrwal #endif 8849249e13SPoonam Aggrwal }; 8949249e13SPoonam Aggrwal 9049249e13SPoonam Aggrwal int num_tlb_entries = ARRAY_SIZE(tlb_table); 91