1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <mpc85xx.h> 8 #include <asm/io.h> 9 #include <ns16550.h> 10 #include <nand.h> 11 #include <asm/mmu.h> 12 #include <asm/immap_85xx.h> 13 #include <fsl_ddr_sdram.h> 14 #include <asm/fsl_law.h> 15 #include <asm/global_data.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 20 void sdram_init(void) 21 { 22 struct ccsr_ddr __iomem *ddr = 23 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; 24 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 25 u32 ddr_ratio; 26 unsigned long ddr_freq_mhz; 27 28 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; 29 ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 30 ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000; 31 32 /* mask off E bit */ 33 u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); 34 35 __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); 36 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); 37 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); 38 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); 39 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); 40 41 if (ddr_freq_mhz < 700) { 42 __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); 43 __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); 44 __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); 45 __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); 46 __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); 47 __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); 48 __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); 49 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); 50 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); 51 } else { 52 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); 53 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); 54 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); 55 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); 56 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); 57 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); 58 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); 59 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); 60 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); 61 } 62 63 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); 64 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); 65 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); 66 67 /* P1014 and it's derivatives support max 16bit DDR width */ 68 if (svr == SVR_P1014) { 69 __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg); 70 __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg); 71 /* For CS0_BNDS we divide the start and end address by 2, so we can just 72 * shift the entire register to achieve the desired result and the mask 73 * the value so we don't write reserved fields */ 74 __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); 75 } 76 77 asm volatile("sync;isync"); 78 udelay(500); 79 80 /* Let the controller go */ 81 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); 82 83 set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); 84 } 85 86 void board_init_f(ulong bootflag) 87 { 88 u32 plat_ratio; 89 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 90 91 /* initialize selected port with appropriate baud rate */ 92 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 93 plat_ratio >>= 1; 94 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; 95 96 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 97 gd->bus_clk / 16 / CONFIG_BAUDRATE); 98 99 puts("\nNAND boot... "); 100 101 /* Initialize the DDR3 */ 102 sdram_init(); 103 104 /* copy code to RAM and jump to it - this should not return */ 105 /* NOTE - code has to be copied out of NAND buffer before 106 * other blocks can be read. 107 */ 108 109 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); 110 } 111 112 void board_init_r(gd_t *gd, ulong dest_addr) 113 { 114 nand_boot(); 115 } 116 117 void putc(char c) 118 { 119 if (c == '\n') 120 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); 121 122 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); 123 } 124 125 void puts(const char *str) 126 { 127 while (*str) 128 putc(*str++); 129 } 130