1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <mpc85xx.h> 8 #include <asm/io.h> 9 #include <ns16550.h> 10 #include <nand.h> 11 #include <asm/mmu.h> 12 #include <asm/immap_85xx.h> 13 #include <asm/fsl_ddr_sdram.h> 14 #include <asm/fsl_law.h> 15 #include <asm/global_data.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 20 void sdram_init(void) 21 { 22 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; 23 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 24 u32 ddr_ratio; 25 unsigned long ddr_freq_mhz; 26 27 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; 28 ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 29 ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000; 30 31 /* mask off E bit */ 32 u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); 33 34 __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); 35 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); 36 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); 37 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); 38 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); 39 40 if (ddr_freq_mhz < 700) { 41 __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); 42 __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); 43 __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); 44 __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); 45 __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); 46 __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); 47 __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); 48 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); 49 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); 50 } else { 51 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); 52 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); 53 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); 54 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); 55 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); 56 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); 57 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); 58 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); 59 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); 60 } 61 62 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); 63 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); 64 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); 65 66 /* P1014 and it's derivatives support max 16bit DDR width */ 67 if (svr == SVR_P1014) { 68 __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg); 69 __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg); 70 /* For CS0_BNDS we divide the start and end address by 2, so we can just 71 * shift the entire register to achieve the desired result and the mask 72 * the value so we don't write reserved fields */ 73 __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); 74 } 75 76 asm volatile("sync;isync"); 77 udelay(500); 78 79 /* Let the controller go */ 80 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); 81 82 set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); 83 } 84 85 void board_init_f(ulong bootflag) 86 { 87 u32 plat_ratio; 88 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 89 90 /* initialize selected port with appropriate baud rate */ 91 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 92 plat_ratio >>= 1; 93 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; 94 95 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 96 gd->bus_clk / 16 / CONFIG_BAUDRATE); 97 98 puts("\nNAND boot... "); 99 100 /* Initialize the DDR3 */ 101 sdram_init(); 102 103 /* copy code to RAM and jump to it - this should not return */ 104 /* NOTE - code has to be copied out of NAND buffer before 105 * other blocks can be read. 106 */ 107 108 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); 109 } 110 111 void board_init_r(gd_t *gd, ulong dest_addr) 112 { 113 nand_boot(); 114 } 115 116 void putc(char c) 117 { 118 if (c == '\n') 119 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); 120 121 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); 122 } 123 124 void puts(const char *str) 125 { 126 while (*str) 127 putc(*str++); 128 } 129