1*0fa934d2SPrabhakar Kushwaha /* 2*0fa934d2SPrabhakar Kushwaha * Copyright 2011 Freescale Semiconductor, Inc. 3*0fa934d2SPrabhakar Kushwaha * 4*0fa934d2SPrabhakar Kushwaha * This program is free software; you can redistribute it and/or 5*0fa934d2SPrabhakar Kushwaha * modify it under the terms of the GNU General Public License as 6*0fa934d2SPrabhakar Kushwaha * published by the Free Software Foundation; either version 2 of 7*0fa934d2SPrabhakar Kushwaha * the License, or (at your option) any later version. 8*0fa934d2SPrabhakar Kushwaha * 9*0fa934d2SPrabhakar Kushwaha * This program is distributed in the hope that it will be useful, 10*0fa934d2SPrabhakar Kushwaha * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*0fa934d2SPrabhakar Kushwaha * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*0fa934d2SPrabhakar Kushwaha * 13*0fa934d2SPrabhakar Kushwaha * GNU General Public License for more details. 14*0fa934d2SPrabhakar Kushwaha * 15*0fa934d2SPrabhakar Kushwaha * You should have received a copy of the GNU General Public License 16*0fa934d2SPrabhakar Kushwaha * along with this program; if not, write to the Free Software 17*0fa934d2SPrabhakar Kushwaha * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18*0fa934d2SPrabhakar Kushwaha * MA 02111-1307 USA 19*0fa934d2SPrabhakar Kushwaha * 20*0fa934d2SPrabhakar Kushwaha */ 21*0fa934d2SPrabhakar Kushwaha #include <common.h> 22*0fa934d2SPrabhakar Kushwaha #include <mpc85xx.h> 23*0fa934d2SPrabhakar Kushwaha #include <asm/io.h> 24*0fa934d2SPrabhakar Kushwaha #include <ns16550.h> 25*0fa934d2SPrabhakar Kushwaha #include <nand.h> 26*0fa934d2SPrabhakar Kushwaha #include <asm/mmu.h> 27*0fa934d2SPrabhakar Kushwaha #include <asm/immap_85xx.h> 28*0fa934d2SPrabhakar Kushwaha #include <asm/fsl_ddr_sdram.h> 29*0fa934d2SPrabhakar Kushwaha #include <asm/fsl_law.h> 30*0fa934d2SPrabhakar Kushwaha #include <asm/global_data.h> 31*0fa934d2SPrabhakar Kushwaha 32*0fa934d2SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 33*0fa934d2SPrabhakar Kushwaha 34*0fa934d2SPrabhakar Kushwaha 35*0fa934d2SPrabhakar Kushwaha void sdram_init(void) 36*0fa934d2SPrabhakar Kushwaha { 37*0fa934d2SPrabhakar Kushwaha ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; 38*0fa934d2SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 39*0fa934d2SPrabhakar Kushwaha u32 ddr_ratio; 40*0fa934d2SPrabhakar Kushwaha unsigned long ddr_freq_mhz; 41*0fa934d2SPrabhakar Kushwaha 42*0fa934d2SPrabhakar Kushwaha ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; 43*0fa934d2SPrabhakar Kushwaha ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 44*0fa934d2SPrabhakar Kushwaha ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; 45*0fa934d2SPrabhakar Kushwaha 46*0fa934d2SPrabhakar Kushwaha /* mask off E bit */ 47*0fa934d2SPrabhakar Kushwaha u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); 48*0fa934d2SPrabhakar Kushwaha 49*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); 50*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); 51*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); 52*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); 53*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); 54*0fa934d2SPrabhakar Kushwaha 55*0fa934d2SPrabhakar Kushwaha if (ddr_freq_mhz < 700) { 56*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); 57*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); 58*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); 59*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); 60*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); 61*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); 62*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); 63*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); 64*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); 65*0fa934d2SPrabhakar Kushwaha } else { 66*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); 67*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); 68*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); 69*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); 70*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); 71*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); 72*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); 73*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); 74*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); 75*0fa934d2SPrabhakar Kushwaha } 76*0fa934d2SPrabhakar Kushwaha 77*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); 78*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); 79*0fa934d2SPrabhakar Kushwaha __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); 80*0fa934d2SPrabhakar Kushwaha 81*0fa934d2SPrabhakar Kushwaha /* P1014 and it's derivatives support max 16bit DDR width */ 82*0fa934d2SPrabhakar Kushwaha if (svr == SVR_P1014) { 83*0fa934d2SPrabhakar Kushwaha __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg); 84*0fa934d2SPrabhakar Kushwaha __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg); 85*0fa934d2SPrabhakar Kushwaha /* For CS0_BNDS we divide the start and end address by 2, so we can just 86*0fa934d2SPrabhakar Kushwaha * shift the entire register to achieve the desired result and the mask 87*0fa934d2SPrabhakar Kushwaha * the value so we don't write reserved fields */ 88*0fa934d2SPrabhakar Kushwaha __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); 89*0fa934d2SPrabhakar Kushwaha } 90*0fa934d2SPrabhakar Kushwaha 91*0fa934d2SPrabhakar Kushwaha asm volatile("sync;isync"); 92*0fa934d2SPrabhakar Kushwaha udelay(500); 93*0fa934d2SPrabhakar Kushwaha 94*0fa934d2SPrabhakar Kushwaha /* Let the controller go */ 95*0fa934d2SPrabhakar Kushwaha out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); 96*0fa934d2SPrabhakar Kushwaha 97*0fa934d2SPrabhakar Kushwaha set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); 98*0fa934d2SPrabhakar Kushwaha } 99*0fa934d2SPrabhakar Kushwaha 100*0fa934d2SPrabhakar Kushwaha void board_init_f(ulong bootflag) 101*0fa934d2SPrabhakar Kushwaha { 102*0fa934d2SPrabhakar Kushwaha u32 plat_ratio; 103*0fa934d2SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 104*0fa934d2SPrabhakar Kushwaha 105*0fa934d2SPrabhakar Kushwaha /* initialize selected port with appropriate baud rate */ 106*0fa934d2SPrabhakar Kushwaha plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 107*0fa934d2SPrabhakar Kushwaha plat_ratio >>= 1; 108*0fa934d2SPrabhakar Kushwaha gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; 109*0fa934d2SPrabhakar Kushwaha 110*0fa934d2SPrabhakar Kushwaha NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 111*0fa934d2SPrabhakar Kushwaha gd->bus_clk / 16 / CONFIG_BAUDRATE); 112*0fa934d2SPrabhakar Kushwaha 113*0fa934d2SPrabhakar Kushwaha puts("\nNAND boot... "); 114*0fa934d2SPrabhakar Kushwaha 115*0fa934d2SPrabhakar Kushwaha /* Initialize the DDR3 */ 116*0fa934d2SPrabhakar Kushwaha sdram_init(); 117*0fa934d2SPrabhakar Kushwaha 118*0fa934d2SPrabhakar Kushwaha /* copy code to RAM and jump to it - this should not return */ 119*0fa934d2SPrabhakar Kushwaha /* NOTE - code has to be copied out of NAND buffer before 120*0fa934d2SPrabhakar Kushwaha * other blocks can be read. 121*0fa934d2SPrabhakar Kushwaha */ 122*0fa934d2SPrabhakar Kushwaha 123*0fa934d2SPrabhakar Kushwaha relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); 124*0fa934d2SPrabhakar Kushwaha } 125*0fa934d2SPrabhakar Kushwaha 126*0fa934d2SPrabhakar Kushwaha void board_init_r(gd_t *gd, ulong dest_addr) 127*0fa934d2SPrabhakar Kushwaha { 128*0fa934d2SPrabhakar Kushwaha nand_boot(); 129*0fa934d2SPrabhakar Kushwaha } 130*0fa934d2SPrabhakar Kushwaha 131*0fa934d2SPrabhakar Kushwaha void putc(char c) 132*0fa934d2SPrabhakar Kushwaha { 133*0fa934d2SPrabhakar Kushwaha if (c == '\n') 134*0fa934d2SPrabhakar Kushwaha NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); 135*0fa934d2SPrabhakar Kushwaha 136*0fa934d2SPrabhakar Kushwaha NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); 137*0fa934d2SPrabhakar Kushwaha } 138*0fa934d2SPrabhakar Kushwaha 139*0fa934d2SPrabhakar Kushwaha void puts(const char *str) 140*0fa934d2SPrabhakar Kushwaha { 141*0fa934d2SPrabhakar Kushwaha while (*str) 142*0fa934d2SPrabhakar Kushwaha putc(*str++); 143*0fa934d2SPrabhakar Kushwaha } 144