1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #include <common.h>
24 #include <asm/processor.h>
25 #include <asm/mmu.h>
26 #include <asm/cache.h>
27 #include <asm/immap_85xx.h>
28 #include <asm/io.h>
29 #include <miiphy.h>
30 #include <libfdt.h>
31 #include <fdt_support.h>
32 #include <fsl_mdio.h>
33 #include <tsec.h>
34 #include <mmc.h>
35 #include <netdev.h>
36 #include <pci.h>
37 #include <asm/fsl_serdes.h>
38 #include <asm/fsl_ifc.h>
39 #include <asm/fsl_pci.h>
40 
41 #ifndef CONFIG_SDCARD
42 #include <hwconfig.h>
43 #endif
44 
45 DECLARE_GLOBAL_DATA_PTR;
46 
47 #define GPIO4_PCIE_RESET_SET		0x08000000
48 #define MUX_CPLD_CAN_UART		0x00
49 #define MUX_CPLD_TDM			0x01
50 #define MUX_CPLD_SPICS0_FLASH		0x00
51 #define MUX_CPLD_SPICS0_SLIC		0x02
52 
53 #ifndef CONFIG_SDCARD
54 struct cpld_data {
55 	u8 cpld_ver; /* cpld revision */
56 	u8 pcba_ver; /* pcb revision number */
57 	u8 twindie_ddr3;
58 	u8 res1[6];
59 	u8 bank_sel; /* NOR Flash bank */
60 	u8 res2[5];
61 	u8 usb2_sel;
62 	u8 res3[1];
63 	u8 porsw_sel;
64 	u8 tdm_can_sel;
65 	u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
66 	u8 por0; /* POR Options */
67 	u8 por1; /* POR Options */
68 	u8 por2; /* POR Options */
69 	u8 por3; /* POR Options */
70 };
71 
72 void cpld_show(void)
73 {
74 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
75 
76 	printf("CPLD: V%x.%x PCBA: V%x.0\n",
77 		in_8(&cpld_data->cpld_ver) & 0xF0,
78 		in_8(&cpld_data->cpld_ver) & 0x0F,
79 		in_8(&cpld_data->pcba_ver) & 0x0F);
80 
81 #ifdef CONFIG_DEBUG
82 	printf("twindie_ddr =%x\n",
83 		in_8(&cpld_data->twindie_ddr3));
84 	printf("bank_sel =%x\n",
85 		in_8(&cpld_data->bank_sel));
86 	printf("usb2_sel =%x\n",
87 		in_8(&cpld_data->usb2_sel));
88 	printf("porsw_sel =%x\n",
89 		in_8(&cpld_data->porsw_sel));
90 	printf("tdm_can_sel =%x\n",
91 		in_8(&cpld_data->tdm_can_sel));
92 	printf("tdm_can_sel =%x\n",
93 		in_8(&cpld_data->tdm_can_sel));
94 	printf("spi_cs0_sel =%x\n",
95 		in_8(&cpld_data->spi_cs0_sel));
96 	printf("bcsr0 =%x\n",
97 		in_8(&cpld_data->bcsr0));
98 	printf("bcsr1 =%x\n",
99 		in_8(&cpld_data->bcsr1));
100 	printf("bcsr2 =%x\n",
101 		in_8(&cpld_data->bcsr2));
102 	printf("bcsr3 =%x\n",
103 		in_8(&cpld_data->bcsr3));
104 #endif
105 }
106 #endif
107 
108 int board_early_init_f(void)
109 {
110 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
111 #ifndef CONFIG_SDCARD
112 	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
113 
114 	/* Clock configuration to access CPLD using IFC(GPCM) */
115 	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
116 #endif
117 	/*
118 	* Reset PCIe slots via GPIO4
119 	*/
120 	setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
121 	setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
122 
123 	return 0;
124 }
125 
126 int board_early_init_r(void)
127 {
128 #ifndef CONFIG_SDCARD
129 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
130 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
131 
132 	/*
133 	 * Remap Boot flash region to caching-inhibited
134 	 * so that flash can be erased properly.
135 	 */
136 
137 	/* Flush d-cache and invalidate i-cache of any FLASH data */
138 	flush_dcache();
139 	invalidate_icache();
140 
141 	/* invalidate existing TLB entry for flash */
142 	disable_tlb(flash_esel);
143 
144 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
145 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
146 			0, flash_esel, BOOKE_PAGESZ_16M, 1);
147 
148 	set_tlb(1, flashbase + 0x1000000,
149 			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
150 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
151 			0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
152 #endif
153 	return 0;
154 }
155 
156 #ifdef CONFIG_PCI
157 void pci_init_board(void)
158 {
159 	fsl_pcie_init_board(0);
160 }
161 #endif /* ifdef CONFIG_PCI */
162 
163 int checkboard(void)
164 {
165 	struct cpu_type *cpu;
166 
167 	cpu = gd->cpu;
168 	printf("Board: %sRDB ", cpu->name);
169 #ifdef CONFIG_PHYS_64BIT
170 	puts("(36-bit addrmap)");
171 #endif
172 	puts("\n");
173 
174 	return 0;
175 }
176 
177 #ifdef CONFIG_TSEC_ENET
178 int board_eth_init(bd_t *bis)
179 {
180 	struct fsl_pq_mdio_info mdio_info;
181 	struct tsec_info_struct tsec_info[4];
182 	struct cpu_type *cpu;
183 	int num = 0;
184 
185 	cpu = gd->cpu;
186 
187 #ifdef CONFIG_TSEC1
188 	SET_STD_TSEC_INFO(tsec_info[num], 1);
189 	num++;
190 #endif
191 #ifdef CONFIG_TSEC2
192 	SET_STD_TSEC_INFO(tsec_info[num], 2);
193 	num++;
194 #endif
195 #ifdef CONFIG_TSEC3
196 	/* P1014 and it's derivatives do not support eTSEC3 */
197 	if (cpu->soc_ver != SVR_P1014 && cpu->soc_ver != SVR_P1014_E) {
198 		SET_STD_TSEC_INFO(tsec_info[num], 3);
199 		num++;
200 	}
201 #endif
202 	if (!num) {
203 		printf("No TSECs initialized\n");
204 		return 0;
205 	}
206 
207 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
208 	mdio_info.name = DEFAULT_MII_NAME;
209 
210 	fsl_pq_mdio_init(bis, &mdio_info);
211 
212 	tsec_eth_init(bis, tsec_info, num);
213 
214 	return pci_eth_init(bis);
215 }
216 #endif
217 
218 #if defined(CONFIG_OF_BOARD_SETUP)
219 void fdt_del_flexcan(void *blob)
220 {
221 	int nodeoff = 0;
222 
223 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
224 				"fsl,flexcan-v1.0")) >= 0) {
225 		fdt_del_node(blob, nodeoff);
226 	}
227 }
228 
229 void fdt_del_spi_flash(void *blob)
230 {
231 	int nodeoff = 0;
232 
233 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
234 				"spansion,s25sl12801")) >= 0) {
235 		fdt_del_node(blob, nodeoff);
236 	}
237 }
238 
239 void fdt_del_spi_slic(void *blob)
240 {
241 	int nodeoff = 0;
242 
243 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
244 				"zarlink,le88266")) >= 0) {
245 		fdt_del_node(blob, nodeoff);
246 	}
247 }
248 
249 void fdt_del_tdm(void *blob)
250 {
251 	int nodeoff = 0;
252 
253 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
254 				"fsl,starlite-tdm")) >= 0) {
255 		fdt_del_node(blob, nodeoff);
256 	}
257 }
258 
259 void ft_board_setup(void *blob, bd_t *bd)
260 {
261 	phys_addr_t base;
262 	phys_size_t size;
263 	struct cpu_type *cpu;
264 
265 	cpu = gd->cpu;
266 
267 	ft_cpu_setup(blob, bd);
268 
269 	base = getenv_bootm_low();
270 	size = getenv_bootm_size();
271 
272 #if defined(CONFIG_PCI)
273 	FT_FSL_PCI_SETUP;
274 #endif
275 
276 	fdt_fixup_memory(blob, (u64)base, (u64)size);
277 
278 #if defined(CONFIG_HAS_FSL_DR_USB)
279 	fdt_fixup_dr_usb(blob, bd);
280 #endif
281 
282        /* P1014 and it's derivatives don't support CAN and eTSEC3 */
283 	if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {
284 		fdt_del_flexcan(blob);
285 		fdt_del_node_and_alias(blob, "ethernet2");
286 	}
287 #ifndef CONFIG_SDCARD
288 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
289 		printf("fdt CAN");
290 		fdt_del_tdm(blob);
291 		fdt_del_spi_slic(blob);
292 	}
293 #ifndef CONFIG_SPIFLASH
294 	else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
295 		printf("fdt TDM");
296 		fdt_del_flexcan(blob);
297 		fdt_del_spi_flash(blob);
298 	}
299 #endif
300 #endif
301 }
302 #endif
303 
304 #ifndef CONFIG_SDCARD
305 int misc_init_r(void)
306 {
307 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
308 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
309 
310 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
311 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
312 				MPC85xx_PMUXCR_CAN1_UART |
313 				MPC85xx_PMUXCR_CAN2_TDM |
314 				MPC85xx_PMUXCR_CAN2_UART);
315 		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
316 	}
317 #ifndef CONFIG_SPIFLASH
318 		if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
319 			printf("TDM");
320 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
321 				MPC85xx_PMUXCR_CAN1_UART);
322 		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
323 				MPC85xx_PMUXCR_CAN1_TDM);
324 		clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
325 		setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
326 		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
327 		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
328 		}
329 #endif
330 	return 0;
331 }
332 #endif
333