1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <asm/processor.h>
8 #include <asm/mmu.h>
9 #include <asm/cache.h>
10 #include <asm/immap_85xx.h>
11 #include <asm/io.h>
12 #include <miiphy.h>
13 #include <linux/libfdt.h>
14 #include <fdt_support.h>
15 #include <fsl_mdio.h>
16 #include <tsec.h>
17 #include <mmc.h>
18 #include <netdev.h>
19 #include <pci.h>
20 #include <asm/fsl_serdes.h>
21 #include <fsl_ifc.h>
22 #include <asm/fsl_pci.h>
23 #include <hwconfig.h>
24 #include <i2c.h>
25 
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 #define GPIO4_PCIE_RESET_SET		0x08000000
29 #define MUX_CPLD_CAN_UART		0x00
30 #define MUX_CPLD_TDM			0x01
31 #define MUX_CPLD_SPICS0_FLASH		0x00
32 #define MUX_CPLD_SPICS0_SLIC		0x02
33 #define PMUXCR1_IFC_MASK       0x00ffff00
34 #define PMUXCR1_SDHC_MASK      0x00fff000
35 #define PMUXCR1_SDHC_ENABLE    0x00555000
36 
37 enum {
38 	MUX_TYPE_IFC,
39 	MUX_TYPE_SDHC,
40 	MUX_TYPE_SPIFLASH,
41 	MUX_TYPE_TDM,
42 	MUX_TYPE_CAN,
43 	MUX_TYPE_CS0_NOR,
44 	MUX_TYPE_CS0_NAND,
45 };
46 
47 enum {
48 	I2C_READ_BANK,
49 	I2C_READ_PCB_VER,
50 };
51 
52 static uint sd_ifc_mux;
53 
54 struct cpld_data {
55 	u8 cpld_ver; /* cpld revision */
56 #if defined(CONFIG_TARGET_P1010RDB_PA)
57 	u8 pcba_ver; /* pcb revision number */
58 	u8 twindie_ddr3;
59 	u8 res1[6];
60 	u8 bank_sel; /* NOR Flash bank */
61 	u8 res2[5];
62 	u8 usb2_sel;
63 	u8 res3[1];
64 	u8 porsw_sel;
65 	u8 tdm_can_sel;
66 	u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
67 	u8 por0; /* POR Options */
68 	u8 por1; /* POR Options */
69 	u8 por2; /* POR Options */
70 	u8 por3; /* POR Options */
71 #elif defined(CONFIG_TARGET_P1010RDB_PB)
72 	u8 rom_loc;
73 #endif
74 };
75 
76 int board_early_init_f(void)
77 {
78 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
79 	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
80 	/* Clock configuration to access CPLD using IFC(GPCM) */
81 	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
82 	/*
83 	* Reset PCIe slots via GPIO4
84 	*/
85 	setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
86 	setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
87 
88 	return 0;
89 }
90 
91 int board_early_init_r(void)
92 {
93 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
94 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
95 
96 	/*
97 	 * Remap Boot flash region to caching-inhibited
98 	 * so that flash can be erased properly.
99 	 */
100 
101 	/* Flush d-cache and invalidate i-cache of any FLASH data */
102 	flush_dcache();
103 	invalidate_icache();
104 
105 	if (flash_esel == -1) {
106 		/* very unlikely unless something is messed up */
107 		puts("Error: Could not find TLB for FLASH BASE\n");
108 		flash_esel = 2;	/* give our best effort to continue */
109 	} else {
110 		/* invalidate existing TLB entry for flash */
111 		disable_tlb(flash_esel);
112 	}
113 
114 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
115 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
116 			0, flash_esel, BOOKE_PAGESZ_16M, 1);
117 
118 	set_tlb(1, flashbase + 0x1000000,
119 			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
120 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
121 			0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
122 	return 0;
123 }
124 
125 #ifdef CONFIG_PCI
126 void pci_init_board(void)
127 {
128 	fsl_pcie_init_board(0);
129 }
130 #endif /* ifdef CONFIG_PCI */
131 
132 int config_board_mux(int ctrl_type)
133 {
134 	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
135 	u8 tmp;
136 
137 #if defined(CONFIG_TARGET_P1010RDB_PA)
138 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
139 
140 	switch (ctrl_type) {
141 	case MUX_TYPE_IFC:
142 		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
143 		tmp = 0xf0;
144 		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
145 		tmp = 0x01;
146 		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
147 		sd_ifc_mux = MUX_TYPE_IFC;
148 		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
149 		break;
150 	case MUX_TYPE_SDHC:
151 		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
152 		tmp = 0xf0;
153 		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
154 		tmp = 0x05;
155 		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
156 		sd_ifc_mux = MUX_TYPE_SDHC;
157 		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
158 				PMUXCR1_SDHC_ENABLE);
159 		break;
160 	case MUX_TYPE_SPIFLASH:
161 		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
162 		break;
163 	case MUX_TYPE_TDM:
164 		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
165 		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
166 		break;
167 	case MUX_TYPE_CAN:
168 		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
169 		break;
170 	default:
171 		break;
172 	}
173 #elif defined(CONFIG_TARGET_P1010RDB_PB)
174 	uint orig_bus = i2c_get_bus_num();
175 	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
176 
177 	switch (ctrl_type) {
178 	case MUX_TYPE_IFC:
179 		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
180 		clrbits_8(&tmp, 0x04);
181 		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
182 		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
183 		clrbits_8(&tmp, 0x04);
184 		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
185 		sd_ifc_mux = MUX_TYPE_IFC;
186 		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
187 		break;
188 	case MUX_TYPE_SDHC:
189 		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
190 		setbits_8(&tmp, 0x04);
191 		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
192 		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
193 		clrbits_8(&tmp, 0x04);
194 		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
195 		sd_ifc_mux = MUX_TYPE_SDHC;
196 		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
197 				PMUXCR1_SDHC_ENABLE);
198 		break;
199 	case MUX_TYPE_SPIFLASH:
200 		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
201 		clrbits_8(&tmp, 0x80);
202 		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
203 		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
204 		clrbits_8(&tmp, 0x80);
205 		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
206 		break;
207 	case MUX_TYPE_TDM:
208 		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
209 		setbits_8(&tmp, 0x82);
210 		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
211 		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
212 		clrbits_8(&tmp, 0x82);
213 		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
214 		break;
215 	case MUX_TYPE_CAN:
216 		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
217 		clrbits_8(&tmp, 0x02);
218 		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
219 		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
220 		clrbits_8(&tmp, 0x02);
221 		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
222 		break;
223 	case MUX_TYPE_CS0_NOR:
224 		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
225 		clrbits_8(&tmp, 0x08);
226 		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
227 		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
228 		clrbits_8(&tmp, 0x08);
229 		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
230 		break;
231 	case MUX_TYPE_CS0_NAND:
232 		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
233 		setbits_8(&tmp, 0x08);
234 		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
235 		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
236 		clrbits_8(&tmp, 0x08);
237 		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
238 		break;
239 	default:
240 		break;
241 	}
242 	i2c_set_bus_num(orig_bus);
243 #endif
244 	return 0;
245 }
246 
247 #ifdef CONFIG_TARGET_P1010RDB_PB
248 int i2c_pca9557_read(int type)
249 {
250 	u8 val;
251 
252 	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
253 	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
254 
255 	switch (type) {
256 	case I2C_READ_BANK:
257 		val = (val & 0x10) >> 4;
258 		break;
259 	case I2C_READ_PCB_VER:
260 		val = ((val & 0x60) >> 5) + 1;
261 		break;
262 	default:
263 		break;
264 	}
265 
266 	return val;
267 }
268 #endif
269 
270 int checkboard(void)
271 {
272 	struct cpu_type *cpu;
273 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
274 	u8 val;
275 
276 	cpu = gd->arch.cpu;
277 #if defined(CONFIG_TARGET_P1010RDB_PA)
278 	printf("Board: %sRDB-PA, ", cpu->name);
279 #elif defined(CONFIG_TARGET_P1010RDB_PB)
280 	printf("Board: %sRDB-PB, ", cpu->name);
281 	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
282 	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
283 	val = 0x0;  /* no polarity inversion */
284 	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
285 #endif
286 
287 #ifdef CONFIG_SDCARD
288 	/* switch to IFC to read info from CPLD */
289 	config_board_mux(MUX_TYPE_IFC);
290 #endif
291 
292 #if defined(CONFIG_TARGET_P1010RDB_PA)
293 	val = (in_8(&cpld_data->pcba_ver) & 0xf);
294 	printf("PCB: v%x.0\n", val);
295 #elif defined(CONFIG_TARGET_P1010RDB_PB)
296 	val = in_8(&cpld_data->cpld_ver);
297 	printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
298 	printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
299 	val = in_8(&cpld_data->rom_loc) & 0xf;
300 	puts("Boot from: ");
301 	switch (val) {
302 	case 0xf:
303 		config_board_mux(MUX_TYPE_CS0_NOR);
304 		printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
305 		break;
306 	case 0xe:
307 		puts("SDHC\n");
308 		val = 0x60; /* set pca9557 pin input/output */
309 		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
310 		break;
311 	case 0x5:
312 		config_board_mux(MUX_TYPE_IFC);
313 		config_board_mux(MUX_TYPE_CS0_NAND);
314 		puts("NAND\n");
315 		break;
316 	case 0x6:
317 		config_board_mux(MUX_TYPE_IFC);
318 		puts("SPI\n");
319 		break;
320 	default:
321 		puts("unknown\n");
322 		break;
323 	}
324 #endif
325 	return 0;
326 }
327 
328 int board_eth_init(bd_t *bis)
329 {
330 #ifdef CONFIG_TSEC_ENET
331 	struct fsl_pq_mdio_info mdio_info;
332 	struct tsec_info_struct tsec_info[4];
333 	struct cpu_type *cpu;
334 	int num = 0;
335 
336 	cpu = gd->arch.cpu;
337 
338 #ifdef CONFIG_TSEC1
339 	SET_STD_TSEC_INFO(tsec_info[num], 1);
340 	num++;
341 #endif
342 #ifdef CONFIG_TSEC2
343 	SET_STD_TSEC_INFO(tsec_info[num], 2);
344 	num++;
345 #endif
346 #ifdef CONFIG_TSEC3
347 	/* P1014 and it's derivatives do not support eTSEC3 */
348 	if (cpu->soc_ver != SVR_P1014) {
349 		SET_STD_TSEC_INFO(tsec_info[num], 3);
350 		num++;
351 	}
352 #endif
353 	if (!num) {
354 		printf("No TSECs initialized\n");
355 		return 0;
356 	}
357 
358 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
359 	mdio_info.name = DEFAULT_MII_NAME;
360 
361 	fsl_pq_mdio_init(bis, &mdio_info);
362 
363 	tsec_eth_init(bis, tsec_info, num);
364 #endif
365 
366 	return pci_eth_init(bis);
367 }
368 
369 #if defined(CONFIG_OF_BOARD_SETUP)
370 void fdt_del_flexcan(void *blob)
371 {
372 	int nodeoff = 0;
373 
374 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
375 				"fsl,p1010-flexcan")) >= 0) {
376 		fdt_del_node(blob, nodeoff);
377 	}
378 }
379 
380 void fdt_del_spi_flash(void *blob)
381 {
382 	int nodeoff = 0;
383 
384 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
385 				"spansion,s25sl12801")) >= 0) {
386 		fdt_del_node(blob, nodeoff);
387 	}
388 }
389 
390 void fdt_del_spi_slic(void *blob)
391 {
392 	int nodeoff = 0;
393 
394 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
395 				"zarlink,le88266")) >= 0) {
396 		fdt_del_node(blob, nodeoff);
397 	}
398 }
399 
400 void fdt_del_tdm(void *blob)
401 {
402 	int nodeoff = 0;
403 
404 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
405 				"fsl,starlite-tdm")) >= 0) {
406 		fdt_del_node(blob, nodeoff);
407 	}
408 }
409 
410 void fdt_del_sdhc(void *blob)
411 {
412 	int nodeoff = 0;
413 
414 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
415 			"fsl,esdhc")) >= 0) {
416 		fdt_del_node(blob, nodeoff);
417 	}
418 }
419 
420 void fdt_del_ifc(void *blob)
421 {
422 	int nodeoff = 0;
423 
424 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
425 				"fsl,ifc")) >= 0) {
426 		fdt_del_node(blob, nodeoff);
427 	}
428 }
429 
430 void fdt_disable_uart1(void *blob)
431 {
432 	int nodeoff;
433 
434 	nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
435 					CONFIG_SYS_NS16550_COM2);
436 
437 	if (nodeoff > 0) {
438 		fdt_status_disabled(blob, nodeoff);
439 	} else {
440 		printf("WARNING unable to set status for fsl,ns16550 "
441 			"uart1: %s\n", fdt_strerror(nodeoff));
442 	}
443 }
444 
445 int ft_board_setup(void *blob, bd_t *bd)
446 {
447 	phys_addr_t base;
448 	phys_size_t size;
449 	struct cpu_type *cpu;
450 
451 	cpu = gd->arch.cpu;
452 
453 	ft_cpu_setup(blob, bd);
454 
455 	base = env_get_bootm_low();
456 	size = env_get_bootm_size();
457 
458 #if defined(CONFIG_PCI)
459 	FT_FSL_PCI_SETUP;
460 #endif
461 
462 	fdt_fixup_memory(blob, (u64)base, (u64)size);
463 
464 #if defined(CONFIG_HAS_FSL_DR_USB)
465 	fsl_fdt_fixup_dr_usb(blob, bd);
466 #endif
467 
468        /* P1014 and it's derivatives don't support CAN and eTSEC3 */
469 	if (cpu->soc_ver == SVR_P1014) {
470 		fdt_del_flexcan(blob);
471 		fdt_del_node_and_alias(blob, "ethernet2");
472 	}
473 
474 	/* Delete IFC node as IFC pins are multiplexing with SDHC */
475 	if (sd_ifc_mux != MUX_TYPE_IFC)
476 		fdt_del_ifc(blob);
477 	else
478 		fdt_del_sdhc(blob);
479 
480 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
481 		fdt_del_tdm(blob);
482 		fdt_del_spi_slic(blob);
483 	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
484 		fdt_del_flexcan(blob);
485 		fdt_del_spi_flash(blob);
486 		fdt_disable_uart1(blob);
487 	} else {
488 		/*
489 		 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
490 		 * explicitly, defaultly spi_cs_sel to spi-flash instead of
491 		 * to tdm/slic.
492 		 */
493 		fdt_del_tdm(blob);
494 		fdt_del_flexcan(blob);
495 		fdt_disable_uart1(blob);
496 	}
497 
498 	return 0;
499 }
500 #endif
501 
502 #ifdef CONFIG_SDCARD
503 int board_mmc_init(bd_t *bis)
504 {
505 	config_board_mux(MUX_TYPE_SDHC);
506 		return -1;
507 }
508 #else
509 void board_reset(void)
510 {
511 	/* mux to IFC to enable CPLD for reset */
512 	if (sd_ifc_mux != MUX_TYPE_IFC)
513 		config_board_mux(MUX_TYPE_IFC);
514 }
515 #endif
516 
517 
518 int misc_init_r(void)
519 {
520 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
521 
522 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
523 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
524 				MPC85xx_PMUXCR_CAN1_UART |
525 				MPC85xx_PMUXCR_CAN2_TDM |
526 				MPC85xx_PMUXCR_CAN2_UART);
527 		config_board_mux(MUX_TYPE_CAN);
528 	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
529 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
530 				MPC85xx_PMUXCR_CAN1_UART);
531 		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
532 				MPC85xx_PMUXCR_CAN1_TDM);
533 		clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
534 		setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
535 		config_board_mux(MUX_TYPE_TDM);
536 	} else {
537 		/* defaultly spi_cs_sel to flash */
538 		config_board_mux(MUX_TYPE_SPIFLASH);
539 	}
540 
541 	if (hwconfig("esdhc"))
542 		config_board_mux(MUX_TYPE_SDHC);
543 	else if (hwconfig("ifc"))
544 		config_board_mux(MUX_TYPE_IFC);
545 
546 #ifdef CONFIG_TARGET_P1010RDB_PB
547 	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
548 #endif
549 	return 0;
550 }
551 
552 #ifndef CONFIG_SPL_BUILD
553 static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
554 				char * const argv[])
555 {
556 	if (argc < 2)
557 		return CMD_RET_USAGE;
558 	if (strcmp(argv[1], "ifc") == 0)
559 		config_board_mux(MUX_TYPE_IFC);
560 	else if (strcmp(argv[1], "sdhc") == 0)
561 		config_board_mux(MUX_TYPE_SDHC);
562 	else
563 		return CMD_RET_USAGE;
564 	return 0;
565 }
566 
567 U_BOOT_CMD(
568 	mux, 2, 0, pin_mux_cmd,
569 	"configure multiplexing pin for IFC/SDHC bus in runtime",
570 	"bus_type (e.g. mux sdhc)"
571 );
572 #endif
573