xref: /openbmc/u-boot/board/freescale/p1010rdb/ddr.c (revision e6469f39)
1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/mmu.h>
9 #include <asm/immap_85xx.h>
10 #include <asm/processor.h>
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/io.h>
14 #include <asm/fsl_law.h>
15 
16 DECLARE_GLOBAL_DATA_PTR;
17 
18 #ifndef CONFIG_SYS_DDR_RAW_TIMING
19 #define CONFIG_SYS_DRAM_SIZE	1024
20 
21 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
22 	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
23 	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
24 	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
25 	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
26 	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
27 	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
28 	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
29 	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
30 	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
31 	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
32 	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
33 	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
34 	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
35 	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
36 	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
37 	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
38 	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
39 	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
40 	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
41 	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
42 	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
43 	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
44 	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
45 	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
46 };
47 
48 fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
49 	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
50 	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
51 	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
52 	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
53 	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
54 	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
55 	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
56 	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
57 	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
58 	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
59 	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
60 	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
61 	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
62 	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
63 	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
64 	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
65 	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
66 	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
67 	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
68 	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
69 	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
70 	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
71 	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
72 	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
73 };
74 
75 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
76 	{750, 850, &ddr_cfg_regs_800},
77 	{607, 749, &ddr_cfg_regs_667},
78 	{0, 0, NULL}
79 };
80 
81 unsigned long get_sdram_size(void)
82 {
83 	struct cpu_type *cpu;
84 	phys_size_t ddr_size;
85 
86 	cpu = gd->arch.cpu;
87 	/* P1014 and it's derivatives support max 16it DDR width */
88 	if (cpu->soc_ver == SVR_P1014)
89 		ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
90 	else
91 		ddr_size = CONFIG_SYS_DRAM_SIZE;
92 
93 	return ddr_size;
94 }
95 
96 /*
97  * Fixed sdram init -- doesn't use serial presence detect.
98  */
99 phys_size_t fixed_sdram(void)
100 {
101 	int i;
102 	char buf[32];
103 	fsl_ddr_cfg_regs_t ddr_cfg_regs;
104 	phys_size_t ddr_size;
105 	ulong ddr_freq, ddr_freq_mhz;
106 	struct cpu_type *cpu;
107 
108 #if defined(CONFIG_SYS_RAMBOOT)
109 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
110 #endif
111 
112 	ddr_freq = get_ddr_freq(0);
113 	ddr_freq_mhz = ddr_freq / 1000000;
114 
115 	printf("Configuring DDR for %s MT/s data rate\n",
116 				strmhz(buf, ddr_freq));
117 
118 	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
119 		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
120 		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
121 			memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
122 							sizeof(ddr_cfg_regs));
123 			break;
124 		}
125 	}
126 
127 	if (fixed_ddr_parm_0[i].max_freq == 0)
128 		panic("Unsupported DDR data rate %s MT/s data rate\n",
129 					strmhz(buf, ddr_freq));
130 
131 	cpu = gd->arch.cpu;
132 	/* P1014 and it's derivatives support max 16bit DDR width */
133 	if (cpu->soc_ver == SVR_P1014) {
134 		ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
135 		ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
136 		/* divide SA and EA by two and then mask the rest so we don't
137 		 * write to reserved fields */
138 		ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
139 	}
140 
141 	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
142 	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
143 
144 	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
145 					LAW_TRGT_IF_DDR_1) < 0) {
146 		printf("ERROR setting Local Access Windows for DDR\n");
147 		return 0;
148 	}
149 
150 	return ddr_size;
151 }
152 
153 #else /* CONFIG_SYS_DDR_RAW_TIMING */
154 /*
155  * Samsung K4B2G0846C-HCF8
156  * The following timing are for "downshift"
157  * i.e. to use CL9 part as CL7
158  * otherwise, tAA, tRCD, tRP will be 13500ps
159  * and tRC will be 49500ps
160  */
161 dimm_params_t ddr_raw_timing = {
162 	.n_ranks = 1,
163 	.rank_density = 1073741824u,
164 	.capacity = 1073741824u,
165 	.primary_sdram_width = 32,
166 	.ec_sdram_width = 0,
167 	.registered_dimm = 0,
168 	.mirrored_dimm = 0,
169 	.n_row_addr = 15,
170 	.n_col_addr = 10,
171 	.n_banks_per_sdram_device = 8,
172 	.edc_config = 0,
173 	.burst_lengths_bitmask = 0x0c,
174 
175 	.tckmin_x_ps = 1875,
176 	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
177 	.taa_ps = 13125,
178 	.twr_ps = 15000,
179 	.trcd_ps = 13125,
180 	.trrd_ps = 7500,
181 	.trp_ps = 13125,
182 	.tras_ps = 37500,
183 	.trc_ps = 50625,
184 	.trfc_ps = 160000,
185 	.twtr_ps = 7500,
186 	.trtp_ps = 7500,
187 	.refresh_rate_ps = 7800000,
188 	.tfaw_ps = 37500,
189 };
190 
191 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
192 		unsigned int controller_number,
193 		unsigned int dimm_number)
194 {
195 	const char dimm_model[] = "Fixed DDR on board";
196 
197 	if ((controller_number == 0) && (dimm_number == 0)) {
198 		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
199 		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
200 		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
201 	}
202 
203 	return 0;
204 }
205 
206 void fsl_ddr_board_options(memctl_options_t *popts,
207 				dimm_params_t *pdimm,
208 				unsigned int ctrl_num)
209 {
210 	struct cpu_type *cpu;
211 	int i;
212 	popts->clk_adjust = 6;
213 	popts->cpo_override = 0x1f;
214 	popts->write_data_delay = 2;
215 	popts->half_strength_driver_enable = 1;
216 	/* Write leveling override */
217 	popts->wrlvl_en = 1;
218 	popts->wrlvl_override = 1;
219 	popts->wrlvl_sample = 0xf;
220 	popts->wrlvl_start = 0x8;
221 	popts->trwt_override = 1;
222 	popts->trwt = 0;
223 
224 	cpu = gd->arch.cpu;
225 	/* P1014 and it's derivatives support max 16it DDR width */
226 	if (cpu->soc_ver == SVR_P1014)
227 		popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
228 
229 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
230 		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
231 		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
232 	}
233 }
234 
235 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
236