1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #include <asm/arch/clock.h> 7 #include <asm/arch/imx-regs.h> 8 #include <asm/arch/mx7-pins.h> 9 #include <asm/arch/sys_proto.h> 10 #include <asm/gpio.h> 11 #include <asm/mach-imx/iomux-v3.h> 12 #include <asm/io.h> 13 #include <linux/sizes.h> 14 #include <common.h> 15 #include <fsl_esdhc.h> 16 #include <mmc.h> 17 #include <miiphy.h> 18 #include <netdev.h> 19 #include <power/pmic.h> 20 #include <power/pfuze3000_pmic.h> 21 #include "../common/pfuze.h" 22 #include <i2c.h> 23 #include <asm/mach-imx/mxc_i2c.h> 24 #include <asm/arch/crm_regs.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 29 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 30 31 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 32 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 33 34 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 35 36 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 37 PAD_CTL_DSE_3P3V_49OHM) 38 39 #define QSPI_PAD_CTRL \ 40 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 41 42 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 43 44 #define SPI_PAD_CTRL \ 45 (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST) 46 47 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) 48 49 #ifdef CONFIG_MXC_SPI 50 static iomux_v3_cfg_t const ecspi3_pads[] = { 51 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 52 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 53 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 54 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 55 }; 56 57 int board_spi_cs_gpio(unsigned bus, unsigned cs) 58 { 59 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1; 60 } 61 62 static void setup_spi(void) 63 { 64 imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); 65 } 66 #endif 67 68 int dram_init(void) 69 { 70 gd->ram_size = PHYS_SDRAM_SIZE; 71 72 return 0; 73 } 74 75 static iomux_v3_cfg_t const wdog_pads[] = { 76 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 77 }; 78 79 static iomux_v3_cfg_t const uart1_pads[] = { 80 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 81 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 82 }; 83 84 #ifdef CONFIG_NAND_MXS 85 static iomux_v3_cfg_t const gpmi_pads[] = { 86 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 87 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 88 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 89 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 90 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 91 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 92 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 93 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 94 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 95 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 96 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 97 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 98 MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 99 MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 100 MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 101 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 102 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 103 MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), 104 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 105 }; 106 107 static void setup_gpmi_nand(void) 108 { 109 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 110 111 /* NAND_USDHC_BUS_CLK is set in rom */ 112 set_clk_nand(); 113 } 114 #endif 115 116 #ifdef CONFIG_VIDEO_MXS 117 static iomux_v3_cfg_t const lcd_pads[] = { 118 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 119 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 120 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 121 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 122 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 123 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 124 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 125 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 126 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 127 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 128 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 129 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 130 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 131 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 132 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 133 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 134 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 135 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 136 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 137 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 138 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 139 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 140 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 141 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 142 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 143 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 144 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 145 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 146 147 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 148 }; 149 150 static iomux_v3_cfg_t const pwm_pads[] = { 151 /* Use GPIO for Brightness adjustment, duty cycle = period */ 152 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 153 }; 154 155 static int setup_lcd(void) 156 { 157 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 158 159 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); 160 161 /* Reset LCD */ 162 gpio_request(IMX_GPIO_NR(3, 4), "lcd reset"); 163 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); 164 udelay(500); 165 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); 166 167 /* Set Brightness to high */ 168 gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight"); 169 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); 170 171 return 0; 172 } 173 #endif 174 175 #ifdef CONFIG_FEC_MXC 176 static iomux_v3_cfg_t const fec1_pads[] = { 177 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 178 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 179 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 180 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 181 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 182 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 183 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 184 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 185 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 186 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 187 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 188 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 189 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 190 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 191 }; 192 193 static void setup_iomux_fec(void) 194 { 195 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 196 } 197 #endif 198 199 static void setup_iomux_uart(void) 200 { 201 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 202 } 203 204 int board_mmc_get_env_dev(int devno) 205 { 206 if (devno == 2) 207 devno--; 208 209 return devno; 210 } 211 212 int mmc_map_to_kernel_blk(int dev_no) 213 { 214 if (dev_no == 1) 215 dev_no++; 216 217 return dev_no; 218 } 219 220 #ifdef CONFIG_FEC_MXC 221 int board_eth_init(bd_t *bis) 222 { 223 int ret; 224 unsigned int gpio; 225 226 ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio); 227 if (ret) { 228 printf("GPIO: 'gpio_spi@0_5' not found\n"); 229 return -ENODEV; 230 } 231 232 ret = gpio_request(gpio, "fec_rst"); 233 if (ret && ret != -EBUSY) { 234 printf("gpio: requesting pin %u failed\n", gpio); 235 return ret; 236 } 237 238 gpio_direction_output(gpio, 0); 239 udelay(500); 240 gpio_direction_output(gpio, 1); 241 242 setup_iomux_fec(); 243 244 ret = fecmxc_initialize_multi(bis, 0, 245 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 246 if (ret) 247 printf("FEC1 MXC: %s:failed\n", __func__); 248 249 return ret; 250 } 251 252 static int setup_fec(void) 253 { 254 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 255 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 256 257 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ 258 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 259 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | 260 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); 261 262 return set_clk_enet(ENET_125MHZ); 263 } 264 265 266 int board_phy_config(struct phy_device *phydev) 267 { 268 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 269 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); 270 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); 271 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); 272 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); 273 274 if (phydev->drv->config) 275 phydev->drv->config(phydev); 276 return 0; 277 } 278 #endif 279 280 #ifdef CONFIG_FSL_QSPI 281 static iomux_v3_cfg_t const quadspi_pads[] = { 282 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 283 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 284 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 285 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 286 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), 287 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), 288 }; 289 290 int board_qspi_init(void) 291 { 292 /* Set the iomux */ 293 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 294 ARRAY_SIZE(quadspi_pads)); 295 296 /* Set the clock */ 297 set_clk_qspi(); 298 299 return 0; 300 } 301 #endif 302 303 int board_early_init_f(void) 304 { 305 setup_iomux_uart(); 306 307 return 0; 308 } 309 310 int board_init(void) 311 { 312 /* address of boot parameters */ 313 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 314 315 #ifdef CONFIG_FEC_MXC 316 setup_fec(); 317 #endif 318 319 #ifdef CONFIG_NAND_MXS 320 setup_gpmi_nand(); 321 #endif 322 323 #ifdef CONFIG_VIDEO_MXS 324 setup_lcd(); 325 #endif 326 327 #ifdef CONFIG_FSL_QSPI 328 board_qspi_init(); 329 #endif 330 331 #ifdef CONFIG_MXC_SPI 332 setup_spi(); 333 #endif 334 335 return 0; 336 } 337 338 #ifdef CONFIG_DM_PMIC 339 int power_init_board(void) 340 { 341 struct udevice *dev; 342 int ret, dev_id, rev_id; 343 344 ret = pmic_get("pfuze3000", &dev); 345 if (ret == -ENODEV) 346 return 0; 347 if (ret != 0) 348 return ret; 349 350 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); 351 rev_id = pmic_reg_read(dev, PFUZE3000_REVID); 352 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); 353 354 pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); 355 356 /* 357 * Set the voltage of VLDO4 output to 2.8V which feeds 358 * the MIPI DSI and MIPI CSI inputs. 359 */ 360 pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); 361 362 return 0; 363 } 364 #endif 365 366 int board_late_init(void) 367 { 368 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 369 370 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 371 372 set_wdog_reset(wdog); 373 374 /* 375 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), 376 * since we use PMIC_PWRON to reset the board. 377 */ 378 clrsetbits_le16(&wdog->wcr, 0, 0x10); 379 380 return 0; 381 } 382 383 int checkboard(void) 384 { 385 char *mode; 386 387 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) 388 mode = "secure"; 389 else 390 mode = "non-secure"; 391 392 printf("Board: i.MX7D SABRESD in %s mode\n", mode); 393 394 return 0; 395 } 396