1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #include <asm/arch/clock.h> 7 #include <asm/arch/imx-regs.h> 8 #include <asm/arch/mx7-pins.h> 9 #include <asm/arch/sys_proto.h> 10 #include <asm/gpio.h> 11 #include <asm/mach-imx/iomux-v3.h> 12 #include <asm/io.h> 13 #include <linux/sizes.h> 14 #include <common.h> 15 #include <fsl_esdhc.h> 16 #include <mmc.h> 17 #include <miiphy.h> 18 #include <netdev.h> 19 #include <power/pmic.h> 20 #include <power/pfuze3000_pmic.h> 21 #include "../common/pfuze.h" 22 #include <i2c.h> 23 #include <asm/mach-imx/mxc_i2c.h> 24 #include <asm/arch/crm_regs.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 29 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 30 31 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 32 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 33 34 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 35 36 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 37 PAD_CTL_DSE_3P3V_49OHM) 38 39 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 40 41 #define SPI_PAD_CTRL \ 42 (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST) 43 44 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) 45 46 #ifdef CONFIG_MXC_SPI 47 static iomux_v3_cfg_t const ecspi3_pads[] = { 48 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 49 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 50 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 51 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 52 }; 53 54 int board_spi_cs_gpio(unsigned bus, unsigned cs) 55 { 56 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1; 57 } 58 59 static void setup_spi(void) 60 { 61 imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); 62 } 63 #endif 64 65 int dram_init(void) 66 { 67 gd->ram_size = PHYS_SDRAM_SIZE; 68 69 return 0; 70 } 71 72 static iomux_v3_cfg_t const wdog_pads[] = { 73 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 74 }; 75 76 static iomux_v3_cfg_t const uart1_pads[] = { 77 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 78 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 79 }; 80 81 #ifdef CONFIG_NAND_MXS 82 static iomux_v3_cfg_t const gpmi_pads[] = { 83 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 84 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 85 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 86 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 87 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 88 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 89 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 90 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 91 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 92 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 93 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 94 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 95 MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 96 MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 97 MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 98 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 99 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 100 MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), 101 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 102 }; 103 104 static void setup_gpmi_nand(void) 105 { 106 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 107 108 /* NAND_USDHC_BUS_CLK is set in rom */ 109 set_clk_nand(); 110 } 111 #endif 112 113 #ifdef CONFIG_VIDEO_MXS 114 static iomux_v3_cfg_t const lcd_pads[] = { 115 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 116 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 117 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 118 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 119 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 120 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 121 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 122 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 123 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 124 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 125 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 126 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 127 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 128 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 129 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 130 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 131 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 132 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 133 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 134 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 135 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 136 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 137 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 138 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 139 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 140 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 141 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 142 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 143 144 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 145 }; 146 147 static iomux_v3_cfg_t const pwm_pads[] = { 148 /* Use GPIO for Brightness adjustment, duty cycle = period */ 149 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 150 }; 151 152 static int setup_lcd(void) 153 { 154 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 155 156 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); 157 158 /* Reset LCD */ 159 gpio_request(IMX_GPIO_NR(3, 4), "lcd reset"); 160 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); 161 udelay(500); 162 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); 163 164 /* Set Brightness to high */ 165 gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight"); 166 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); 167 168 return 0; 169 } 170 #endif 171 172 #ifdef CONFIG_FEC_MXC 173 static iomux_v3_cfg_t const fec1_pads[] = { 174 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 175 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 176 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 177 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 178 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 179 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 180 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 181 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 182 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 183 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 184 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 185 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 186 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 187 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 188 }; 189 190 static void setup_iomux_fec(void) 191 { 192 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 193 } 194 #endif 195 196 static void setup_iomux_uart(void) 197 { 198 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 199 } 200 201 int board_mmc_get_env_dev(int devno) 202 { 203 if (devno == 2) 204 devno--; 205 206 return devno; 207 } 208 209 int mmc_map_to_kernel_blk(int dev_no) 210 { 211 if (dev_no == 1) 212 dev_no++; 213 214 return dev_no; 215 } 216 217 #ifdef CONFIG_FEC_MXC 218 int board_eth_init(bd_t *bis) 219 { 220 int ret; 221 unsigned int gpio; 222 223 ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio); 224 if (ret) { 225 printf("GPIO: 'gpio_spi@0_5' not found\n"); 226 return -ENODEV; 227 } 228 229 ret = gpio_request(gpio, "fec_rst"); 230 if (ret && ret != -EBUSY) { 231 printf("gpio: requesting pin %u failed\n", gpio); 232 return ret; 233 } 234 235 gpio_direction_output(gpio, 0); 236 udelay(500); 237 gpio_direction_output(gpio, 1); 238 239 setup_iomux_fec(); 240 241 ret = fecmxc_initialize_multi(bis, 0, 242 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 243 if (ret) 244 printf("FEC1 MXC: %s:failed\n", __func__); 245 246 return ret; 247 } 248 249 static int setup_fec(void) 250 { 251 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 252 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 253 254 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ 255 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 256 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | 257 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); 258 259 return set_clk_enet(ENET_125MHZ); 260 } 261 262 263 int board_phy_config(struct phy_device *phydev) 264 { 265 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 266 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); 267 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); 268 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); 269 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); 270 271 if (phydev->drv->config) 272 phydev->drv->config(phydev); 273 return 0; 274 } 275 #endif 276 277 #ifdef CONFIG_FSL_QSPI 278 int board_qspi_init(void) 279 { 280 /* Set the clock */ 281 set_clk_qspi(); 282 283 return 0; 284 } 285 #endif 286 287 int board_early_init_f(void) 288 { 289 setup_iomux_uart(); 290 291 return 0; 292 } 293 294 int board_init(void) 295 { 296 /* address of boot parameters */ 297 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 298 299 #ifdef CONFIG_FEC_MXC 300 setup_fec(); 301 #endif 302 303 #ifdef CONFIG_NAND_MXS 304 setup_gpmi_nand(); 305 #endif 306 307 #ifdef CONFIG_VIDEO_MXS 308 setup_lcd(); 309 #endif 310 311 #ifdef CONFIG_FSL_QSPI 312 board_qspi_init(); 313 #endif 314 315 #ifdef CONFIG_MXC_SPI 316 setup_spi(); 317 #endif 318 319 return 0; 320 } 321 322 #ifdef CONFIG_DM_PMIC 323 int power_init_board(void) 324 { 325 struct udevice *dev; 326 int ret, dev_id, rev_id; 327 328 ret = pmic_get("pfuze3000", &dev); 329 if (ret == -ENODEV) 330 return 0; 331 if (ret != 0) 332 return ret; 333 334 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); 335 rev_id = pmic_reg_read(dev, PFUZE3000_REVID); 336 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); 337 338 pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); 339 340 /* 341 * Set the voltage of VLDO4 output to 2.8V which feeds 342 * the MIPI DSI and MIPI CSI inputs. 343 */ 344 pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); 345 346 return 0; 347 } 348 #endif 349 350 int board_late_init(void) 351 { 352 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 353 354 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 355 356 set_wdog_reset(wdog); 357 358 /* 359 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), 360 * since we use PMIC_PWRON to reset the board. 361 */ 362 clrsetbits_le16(&wdog->wcr, 0, 0x10); 363 364 return 0; 365 } 366 367 int checkboard(void) 368 { 369 char *mode; 370 371 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) 372 mode = "secure"; 373 else 374 mode = "non-secure"; 375 376 printf("Board: i.MX7D SABRESD in %s mode\n", mode); 377 378 return 0; 379 } 380