1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/mx7-pins.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/gpio.h> 12 #include <asm/imx-common/iomux-v3.h> 13 #include <asm/io.h> 14 #include <linux/sizes.h> 15 #include <common.h> 16 #include <fsl_esdhc.h> 17 #include <mmc.h> 18 #include <miiphy.h> 19 #include <netdev.h> 20 #include <power/pmic.h> 21 #include <power/pfuze3000_pmic.h> 22 #include "../common/pfuze.h" 23 #include <i2c.h> 24 #include <asm/imx-common/mxc_i2c.h> 25 #include <asm/arch/crm_regs.h> 26 #include <usb/ehci-fsl.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 31 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 32 33 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 34 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 35 36 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 37 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 38 39 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 40 41 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 42 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) 43 44 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 45 PAD_CTL_DSE_3P3V_49OHM) 46 47 #define QSPI_PAD_CTRL \ 48 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 49 50 #ifdef CONFIG_SYS_I2C_MXC 51 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 52 /* I2C1 for PMIC */ 53 static struct i2c_pads_info i2c_pad_info1 = { 54 .scl = { 55 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, 56 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, 57 .gp = IMX_GPIO_NR(4, 8), 58 }, 59 .sda = { 60 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, 61 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, 62 .gp = IMX_GPIO_NR(4, 9), 63 }, 64 }; 65 #endif 66 67 int dram_init(void) 68 { 69 gd->ram_size = PHYS_SDRAM_SIZE; 70 71 return 0; 72 } 73 74 static iomux_v3_cfg_t const wdog_pads[] = { 75 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 76 }; 77 78 static iomux_v3_cfg_t const uart1_pads[] = { 79 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 80 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 81 }; 82 83 static iomux_v3_cfg_t const usdhc1_pads[] = { 84 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 91 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 }; 94 95 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { 96 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 97 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 98 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 99 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 100 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 102 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 103 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 108 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 109 }; 110 111 #define IOX_SDI IMX_GPIO_NR(1, 9) 112 #define IOX_STCP IMX_GPIO_NR(1, 12) 113 #define IOX_SHCP IMX_GPIO_NR(1, 13) 114 115 static iomux_v3_cfg_t const iox_pads[] = { 116 /* IOX_SDI */ 117 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), 118 /* IOX_STCP */ 119 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 120 /* IOX_SHCP */ 121 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), 122 }; 123 124 /* 125 * PCIE_DIS_B --> Q0 126 * PCIE_RST_B --> Q1 127 * HDMI_RST_B --> Q2 128 * PERI_RST_B --> Q3 129 * SENSOR_RST_B --> Q4 130 * ENET_RST_B --> Q5 131 * PERI_3V3_EN --> Q6 132 * LCD_PWR_EN --> Q7 133 */ 134 enum qn { 135 PCIE_DIS_B, 136 PCIE_RST_B, 137 HDMI_RST_B, 138 PERI_RST_B, 139 SENSOR_RST_B, 140 ENET_RST_B, 141 PERI_3V3_EN, 142 LCD_PWR_EN, 143 }; 144 145 enum qn_func { 146 qn_reset, 147 qn_enable, 148 qn_disable, 149 }; 150 151 enum qn_level { 152 qn_low = 0, 153 qn_high = 1, 154 }; 155 156 static enum qn_level seq[3][2] = { 157 {0, 1}, {1, 1}, {0, 0} 158 }; 159 160 static enum qn_func qn_output[8] = { 161 qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, 162 qn_enable 163 }; 164 165 static void iox74lv_init(void) 166 { 167 int i; 168 169 for (i = 7; i >= 0; i--) { 170 gpio_direction_output(IOX_SHCP, 0); 171 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 172 udelay(500); 173 gpio_direction_output(IOX_SHCP, 1); 174 udelay(500); 175 } 176 177 gpio_direction_output(IOX_STCP, 0); 178 udelay(500); 179 /* 180 * shift register will be output to pins 181 */ 182 gpio_direction_output(IOX_STCP, 1); 183 184 for (i = 7; i >= 0; i--) { 185 gpio_direction_output(IOX_SHCP, 0); 186 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 187 udelay(500); 188 gpio_direction_output(IOX_SHCP, 1); 189 udelay(500); 190 } 191 gpio_direction_output(IOX_STCP, 0); 192 udelay(500); 193 /* 194 * shift register will be output to pins 195 */ 196 gpio_direction_output(IOX_STCP, 1); 197 }; 198 199 #ifdef CONFIG_VIDEO_MXS 200 static iomux_v3_cfg_t const lcd_pads[] = { 201 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 202 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 203 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 204 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 205 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 206 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 207 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 208 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 209 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 210 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 211 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 212 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 213 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 214 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 215 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 216 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 217 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 218 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 219 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 220 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 221 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 222 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 223 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 224 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 225 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 226 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 227 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 228 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 229 230 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 231 }; 232 233 static iomux_v3_cfg_t const pwm_pads[] = { 234 /* Use GPIO for Brightness adjustment, duty cycle = period */ 235 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 236 }; 237 238 static int setup_lcd(void) 239 { 240 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 241 242 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); 243 244 /* Reset LCD */ 245 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); 246 udelay(500); 247 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); 248 249 /* Set Brightness to high */ 250 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); 251 252 return 0; 253 } 254 #endif 255 256 #ifdef CONFIG_FEC_MXC 257 static iomux_v3_cfg_t const fec1_pads[] = { 258 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 259 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 260 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 261 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 262 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 263 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 264 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 265 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 266 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 267 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 268 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 269 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 270 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 271 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 272 }; 273 274 static void setup_iomux_fec(void) 275 { 276 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 277 } 278 #endif 279 280 static void setup_iomux_uart(void) 281 { 282 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 283 } 284 285 #ifdef CONFIG_FSL_ESDHC 286 287 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) 288 #define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) 289 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) 290 291 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 292 {USDHC1_BASE_ADDR, 0, 4}, 293 {USDHC3_BASE_ADDR}, 294 }; 295 296 static int mmc_get_env_devno(void) 297 { 298 struct bootrom_sw_info **p = 299 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; 300 301 u8 boot_type = (*p)->boot_dev_type; 302 u8 dev_no = (*p)->boot_dev_instance; 303 304 /* If not boot from sd/mmc, use default value */ 305 if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) 306 return CONFIG_SYS_MMC_ENV_DEV; 307 308 if (dev_no == 2) 309 dev_no--; 310 311 return dev_no; 312 } 313 314 static int mmc_map_to_kernel_blk(int dev_no) 315 { 316 if (dev_no == 1) 317 dev_no++; 318 319 return dev_no; 320 } 321 322 int board_mmc_getcd(struct mmc *mmc) 323 { 324 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 325 int ret = 0; 326 327 switch (cfg->esdhc_base) { 328 case USDHC1_BASE_ADDR: 329 ret = !gpio_get_value(USDHC1_CD_GPIO); 330 break; 331 case USDHC3_BASE_ADDR: 332 ret = 1; /* Assume uSDHC3 emmc is always present */ 333 break; 334 } 335 336 return ret; 337 } 338 339 int board_mmc_init(bd_t *bis) 340 { 341 int i, ret; 342 /* 343 * According to the board_mmc_init() the following map is done: 344 * (U-boot device node) (Physical Port) 345 * mmc0 USDHC1 346 * mmc2 USDHC3 (eMMC) 347 */ 348 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 349 switch (i) { 350 case 0: 351 imx_iomux_v3_setup_multiple_pads( 352 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 353 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 354 gpio_direction_input(USDHC1_CD_GPIO); 355 gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); 356 gpio_direction_output(USDHC1_PWR_GPIO, 0); 357 udelay(500); 358 gpio_direction_output(USDHC1_PWR_GPIO, 1); 359 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 360 break; 361 case 1: 362 imx_iomux_v3_setup_multiple_pads( 363 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); 364 gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); 365 gpio_direction_output(USDHC3_PWR_GPIO, 0); 366 udelay(500); 367 gpio_direction_output(USDHC3_PWR_GPIO, 1); 368 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 369 break; 370 default: 371 printf("Warning: you configured more USDHC controllers" 372 "(%d) than supported by the board\n", i + 1); 373 return -EINVAL; 374 } 375 376 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 377 if (ret) 378 return ret; 379 } 380 381 return 0; 382 } 383 384 static int check_mmc_autodetect(void) 385 { 386 char *autodetect_str = getenv("mmcautodetect"); 387 388 if ((autodetect_str != NULL) && 389 (strcmp(autodetect_str, "yes") == 0)) { 390 return 1; 391 } 392 393 return 0; 394 } 395 396 static void mmc_late_init(void) 397 { 398 char cmd[32]; 399 char mmcblk[32]; 400 u32 dev_no = mmc_get_env_devno(); 401 402 if (!check_mmc_autodetect()) 403 return; 404 405 setenv_ulong("mmcdev", dev_no); 406 407 /* Set mmcblk env */ 408 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", 409 mmc_map_to_kernel_blk(dev_no)); 410 setenv("mmcroot", mmcblk); 411 412 sprintf(cmd, "mmc dev %d", dev_no); 413 run_command(cmd, 0); 414 } 415 416 #endif 417 418 #ifdef CONFIG_FEC_MXC 419 int board_eth_init(bd_t *bis) 420 { 421 int ret; 422 423 setup_iomux_fec(); 424 425 ret = fecmxc_initialize_multi(bis, 0, 426 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 427 if (ret) 428 printf("FEC1 MXC: %s:failed\n", __func__); 429 430 return ret; 431 } 432 433 static int setup_fec(void) 434 { 435 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 436 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 437 438 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ 439 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 440 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | 441 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); 442 443 return set_clk_enet(ENET_125MHz); 444 } 445 446 447 int board_phy_config(struct phy_device *phydev) 448 { 449 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 450 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); 451 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); 452 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); 453 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); 454 455 if (phydev->drv->config) 456 phydev->drv->config(phydev); 457 return 0; 458 } 459 #endif 460 461 #ifdef CONFIG_FSL_QSPI 462 static iomux_v3_cfg_t const quadspi_pads[] = { 463 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 464 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 465 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 466 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 467 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), 468 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), 469 }; 470 471 int board_qspi_init(void) 472 { 473 /* Set the iomux */ 474 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 475 ARRAY_SIZE(quadspi_pads)); 476 477 /* Set the clock */ 478 set_clk_qspi(); 479 480 return 0; 481 } 482 #endif 483 484 int board_early_init_f(void) 485 { 486 setup_iomux_uart(); 487 488 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 489 490 return 0; 491 } 492 493 int board_init(void) 494 { 495 /* address of boot parameters */ 496 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 497 498 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 499 500 iox74lv_init(); 501 502 #ifdef CONFIG_FEC_MXC 503 setup_fec(); 504 #endif 505 506 #ifdef CONFIG_VIDEO_MXS 507 setup_lcd(); 508 #endif 509 510 #ifdef CONFIG_FSL_QSPI 511 board_qspi_init(); 512 #endif 513 514 return 0; 515 } 516 517 #ifdef CONFIG_POWER 518 #define I2C_PMIC 0 519 int power_init_board(void) 520 { 521 struct pmic *p; 522 int ret; 523 unsigned int reg, rev_id; 524 525 ret = power_pfuze3000_init(I2C_PMIC); 526 if (ret) 527 return ret; 528 529 p = pmic_get("PFUZE3000"); 530 ret = pmic_probe(p); 531 if (ret) 532 return ret; 533 534 pmic_reg_read(p, PFUZE3000_DEVICEID, ®); 535 pmic_reg_read(p, PFUZE3000_REVID, &rev_id); 536 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); 537 538 /* disable Low Power Mode during standby mode */ 539 pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); 540 reg |= 0x1; 541 pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); 542 543 return 0; 544 } 545 #endif 546 547 int board_late_init(void) 548 { 549 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 550 551 #ifdef CONFIG_ENV_IS_IN_MMC 552 mmc_late_init(); 553 #endif 554 555 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 556 557 set_wdog_reset(wdog); 558 559 /* 560 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), 561 * since we use PMIC_PWRON to reset the board. 562 */ 563 clrsetbits_le16(&wdog->wcr, 0, 0x10); 564 565 return 0; 566 } 567 568 int checkboard(void) 569 { 570 puts("Board: i.MX7D SABRESD\n"); 571 572 return 0; 573 } 574 575 #ifdef CONFIG_USB_EHCI_MX7 576 static iomux_v3_cfg_t const usb_otg1_pads[] = { 577 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 578 }; 579 580 static iomux_v3_cfg_t const usb_otg2_pads[] = { 581 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 582 }; 583 584 int board_ehci_hcd_init(int port) 585 { 586 switch (port) { 587 case 0: 588 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, 589 ARRAY_SIZE(usb_otg1_pads)); 590 break; 591 case 1: 592 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 593 ARRAY_SIZE(usb_otg2_pads)); 594 break; 595 default: 596 printf("MXC USB port %d not yet supported\n", port); 597 return -EINVAL; 598 } 599 return 0; 600 } 601 #endif 602