1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/mx7-pins.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/gpio.h> 12 #include <asm/imx-common/iomux-v3.h> 13 #include <asm/io.h> 14 #include <linux/sizes.h> 15 #include <common.h> 16 #include <fsl_esdhc.h> 17 #include <mmc.h> 18 #include <miiphy.h> 19 #include <netdev.h> 20 #include <power/pmic.h> 21 #include <power/pfuze3000_pmic.h> 22 #include "../common/pfuze.h" 23 #include <i2c.h> 24 #include <asm/imx-common/mxc_i2c.h> 25 #include <asm/arch/crm_regs.h> 26 #include <usb/ehci-fsl.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 31 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 32 33 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 34 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 35 36 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 37 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 38 39 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 40 41 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 42 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) 43 44 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 45 PAD_CTL_DSE_3P3V_49OHM) 46 47 #ifdef CONFIG_SYS_I2C_MXC 48 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 49 /* I2C1 for PMIC */ 50 static struct i2c_pads_info i2c_pad_info1 = { 51 .scl = { 52 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, 53 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, 54 .gp = IMX_GPIO_NR(4, 8), 55 }, 56 .sda = { 57 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, 58 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, 59 .gp = IMX_GPIO_NR(4, 9), 60 }, 61 }; 62 #endif 63 64 int dram_init(void) 65 { 66 gd->ram_size = PHYS_SDRAM_SIZE; 67 68 return 0; 69 } 70 71 static iomux_v3_cfg_t const wdog_pads[] = { 72 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 73 }; 74 75 static iomux_v3_cfg_t const uart1_pads[] = { 76 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 77 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 78 }; 79 80 static iomux_v3_cfg_t const usdhc1_pads[] = { 81 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 82 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 83 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 88 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 }; 91 92 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { 93 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 94 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 95 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 96 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 97 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 98 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 99 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 100 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 102 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 103 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 105 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 }; 107 108 #define IOX_SDI IMX_GPIO_NR(1, 9) 109 #define IOX_STCP IMX_GPIO_NR(1, 12) 110 #define IOX_SHCP IMX_GPIO_NR(1, 13) 111 112 static iomux_v3_cfg_t const iox_pads[] = { 113 /* IOX_SDI */ 114 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), 115 /* IOX_STCP */ 116 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 117 /* IOX_SHCP */ 118 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), 119 }; 120 121 /* 122 * PCIE_DIS_B --> Q0 123 * PCIE_RST_B --> Q1 124 * HDMI_RST_B --> Q2 125 * PERI_RST_B --> Q3 126 * SENSOR_RST_B --> Q4 127 * ENET_RST_B --> Q5 128 * PERI_3V3_EN --> Q6 129 * LCD_PWR_EN --> Q7 130 */ 131 enum qn { 132 PCIE_DIS_B, 133 PCIE_RST_B, 134 HDMI_RST_B, 135 PERI_RST_B, 136 SENSOR_RST_B, 137 ENET_RST_B, 138 PERI_3V3_EN, 139 LCD_PWR_EN, 140 }; 141 142 enum qn_func { 143 qn_reset, 144 qn_enable, 145 qn_disable, 146 }; 147 148 enum qn_level { 149 qn_low = 0, 150 qn_high = 1, 151 }; 152 153 static enum qn_level seq[3][2] = { 154 {0, 1}, {1, 1}, {0, 0} 155 }; 156 157 static enum qn_func qn_output[8] = { 158 qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, 159 qn_enable 160 }; 161 162 static void iox74lv_init(void) 163 { 164 int i; 165 166 for (i = 7; i >= 0; i--) { 167 gpio_direction_output(IOX_SHCP, 0); 168 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 169 udelay(500); 170 gpio_direction_output(IOX_SHCP, 1); 171 udelay(500); 172 } 173 174 gpio_direction_output(IOX_STCP, 0); 175 udelay(500); 176 /* 177 * shift register will be output to pins 178 */ 179 gpio_direction_output(IOX_STCP, 1); 180 181 for (i = 7; i >= 0; i--) { 182 gpio_direction_output(IOX_SHCP, 0); 183 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 184 udelay(500); 185 gpio_direction_output(IOX_SHCP, 1); 186 udelay(500); 187 } 188 gpio_direction_output(IOX_STCP, 0); 189 udelay(500); 190 /* 191 * shift register will be output to pins 192 */ 193 gpio_direction_output(IOX_STCP, 1); 194 }; 195 196 #ifdef CONFIG_VIDEO_MXS 197 static iomux_v3_cfg_t const lcd_pads[] = { 198 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 199 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 200 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 201 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 202 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 203 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 204 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 205 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 206 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 207 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 208 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 209 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 210 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 211 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 212 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 213 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 214 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 215 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 216 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 217 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 218 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 219 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 220 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 221 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 222 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 223 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 224 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 225 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 226 227 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 228 }; 229 230 static iomux_v3_cfg_t const pwm_pads[] = { 231 /* Use GPIO for Brightness adjustment, duty cycle = period */ 232 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 233 }; 234 235 static int setup_lcd(void) 236 { 237 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 238 239 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); 240 241 /* Reset LCD */ 242 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); 243 udelay(500); 244 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); 245 246 /* Set Brightness to high */ 247 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); 248 249 return 0; 250 } 251 #endif 252 253 #ifdef CONFIG_FEC_MXC 254 static iomux_v3_cfg_t const fec1_pads[] = { 255 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 256 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 257 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 258 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 259 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 260 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 261 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 262 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 263 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 264 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 265 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 266 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 267 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 268 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 269 }; 270 271 static void setup_iomux_fec(void) 272 { 273 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 274 } 275 #endif 276 277 static void setup_iomux_uart(void) 278 { 279 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 280 } 281 282 #ifdef CONFIG_FSL_ESDHC 283 284 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) 285 #define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) 286 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) 287 288 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 289 {USDHC1_BASE_ADDR, 0, 4}, 290 {USDHC3_BASE_ADDR}, 291 }; 292 293 static int mmc_get_env_devno(void) 294 { 295 struct bootrom_sw_info **p = 296 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; 297 298 u8 boot_type = (*p)->boot_dev_type; 299 u8 dev_no = (*p)->boot_dev_instance; 300 301 /* If not boot from sd/mmc, use default value */ 302 if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) 303 return CONFIG_SYS_MMC_ENV_DEV; 304 305 if (dev_no == 2) 306 dev_no--; 307 308 return dev_no; 309 } 310 311 static int mmc_map_to_kernel_blk(int dev_no) 312 { 313 if (dev_no == 1) 314 dev_no++; 315 316 return dev_no; 317 } 318 319 int board_mmc_getcd(struct mmc *mmc) 320 { 321 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 322 int ret = 0; 323 324 switch (cfg->esdhc_base) { 325 case USDHC1_BASE_ADDR: 326 ret = !gpio_get_value(USDHC1_CD_GPIO); 327 break; 328 case USDHC3_BASE_ADDR: 329 ret = 1; /* Assume uSDHC3 emmc is always present */ 330 break; 331 } 332 333 return ret; 334 } 335 336 int board_mmc_init(bd_t *bis) 337 { 338 int i, ret; 339 /* 340 * According to the board_mmc_init() the following map is done: 341 * (U-boot device node) (Physical Port) 342 * mmc0 USDHC1 343 * mmc2 USDHC3 (eMMC) 344 */ 345 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 346 switch (i) { 347 case 0: 348 imx_iomux_v3_setup_multiple_pads( 349 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 350 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 351 gpio_direction_input(USDHC1_CD_GPIO); 352 gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); 353 gpio_direction_output(USDHC1_PWR_GPIO, 0); 354 udelay(500); 355 gpio_direction_output(USDHC1_PWR_GPIO, 1); 356 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 357 break; 358 case 1: 359 imx_iomux_v3_setup_multiple_pads( 360 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); 361 gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); 362 gpio_direction_output(USDHC3_PWR_GPIO, 0); 363 udelay(500); 364 gpio_direction_output(USDHC3_PWR_GPIO, 1); 365 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 366 break; 367 default: 368 printf("Warning: you configured more USDHC controllers" 369 "(%d) than supported by the board\n", i + 1); 370 return -EINVAL; 371 } 372 373 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 374 if (ret) 375 return ret; 376 } 377 378 return 0; 379 } 380 381 static int check_mmc_autodetect(void) 382 { 383 char *autodetect_str = getenv("mmcautodetect"); 384 385 if ((autodetect_str != NULL) && 386 (strcmp(autodetect_str, "yes") == 0)) { 387 return 1; 388 } 389 390 return 0; 391 } 392 393 static void mmc_late_init(void) 394 { 395 char cmd[32]; 396 char mmcblk[32]; 397 u32 dev_no = mmc_get_env_devno(); 398 399 if (!check_mmc_autodetect()) 400 return; 401 402 setenv_ulong("mmcdev", dev_no); 403 404 /* Set mmcblk env */ 405 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", 406 mmc_map_to_kernel_blk(dev_no)); 407 setenv("mmcroot", mmcblk); 408 409 sprintf(cmd, "mmc dev %d", dev_no); 410 run_command(cmd, 0); 411 } 412 413 #endif 414 415 #ifdef CONFIG_FEC_MXC 416 int board_eth_init(bd_t *bis) 417 { 418 int ret; 419 420 setup_iomux_fec(); 421 422 ret = fecmxc_initialize_multi(bis, 0, 423 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 424 if (ret) 425 printf("FEC1 MXC: %s:failed\n", __func__); 426 427 return ret; 428 } 429 430 static int setup_fec(void) 431 { 432 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 433 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 434 435 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ 436 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 437 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | 438 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); 439 440 return set_clk_enet(ENET_125MHz); 441 } 442 443 444 int board_phy_config(struct phy_device *phydev) 445 { 446 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 447 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); 448 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); 449 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); 450 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); 451 452 if (phydev->drv->config) 453 phydev->drv->config(phydev); 454 return 0; 455 } 456 #endif 457 458 int board_early_init_f(void) 459 { 460 setup_iomux_uart(); 461 462 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 463 464 return 0; 465 } 466 467 int board_init(void) 468 { 469 /* address of boot parameters */ 470 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 471 472 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 473 474 iox74lv_init(); 475 476 #ifdef CONFIG_FEC_MXC 477 setup_fec(); 478 #endif 479 480 #ifdef CONFIG_VIDEO_MXS 481 setup_lcd(); 482 #endif 483 484 return 0; 485 } 486 487 #ifdef CONFIG_POWER 488 #define I2C_PMIC 0 489 int power_init_board(void) 490 { 491 struct pmic *p; 492 int ret; 493 unsigned int reg, rev_id; 494 495 ret = power_pfuze3000_init(I2C_PMIC); 496 if (ret) 497 return ret; 498 499 p = pmic_get("PFUZE3000"); 500 ret = pmic_probe(p); 501 if (ret) 502 return ret; 503 504 pmic_reg_read(p, PFUZE3000_DEVICEID, ®); 505 pmic_reg_read(p, PFUZE3000_REVID, &rev_id); 506 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); 507 508 /* disable Low Power Mode during standby mode */ 509 pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); 510 reg |= 0x1; 511 pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); 512 513 return 0; 514 } 515 #endif 516 517 int board_late_init(void) 518 { 519 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 520 521 #ifdef CONFIG_ENV_IS_IN_MMC 522 mmc_late_init(); 523 #endif 524 525 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 526 527 set_wdog_reset(wdog); 528 529 /* 530 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), 531 * since we use PMIC_PWRON to reset the board. 532 */ 533 clrsetbits_le16(&wdog->wcr, 0, 0x10); 534 535 return 0; 536 } 537 538 int checkboard(void) 539 { 540 puts("Board: i.MX7D SABRESD\n"); 541 542 return 0; 543 } 544 545 #ifdef CONFIG_USB_EHCI_MX7 546 static iomux_v3_cfg_t const usb_otg1_pads[] = { 547 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 548 }; 549 550 static iomux_v3_cfg_t const usb_otg2_pads[] = { 551 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 552 }; 553 554 int board_ehci_hcd_init(int port) 555 { 556 switch (port) { 557 case 0: 558 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, 559 ARRAY_SIZE(usb_otg1_pads)); 560 break; 561 case 1: 562 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 563 ARRAY_SIZE(usb_otg2_pads)); 564 break; 565 default: 566 printf("MXC USB port %d not yet supported\n", port); 567 return -EINVAL; 568 } 569 return 0; 570 } 571 #endif 572