1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/mx7-pins.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/gpio.h> 12 #include <asm/imx-common/iomux-v3.h> 13 #include <asm/imx-common/boot_mode.h> 14 #include <asm/io.h> 15 #include <linux/sizes.h> 16 #include <common.h> 17 #include <fsl_esdhc.h> 18 #include <mmc.h> 19 #include <miiphy.h> 20 #include <netdev.h> 21 #include <power/pmic.h> 22 #include <power/pfuze3000_pmic.h> 23 #include "../common/pfuze.h" 24 #include <i2c.h> 25 #include <asm/imx-common/mxc_i2c.h> 26 #include <asm/arch/crm_regs.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 31 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 32 33 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 34 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 35 36 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 37 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 38 39 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 40 41 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 42 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) 43 44 #ifdef CONFIG_SYS_I2C_MXC 45 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 46 /* I2C1 for PMIC */ 47 struct i2c_pads_info i2c_pad_info1 = { 48 .scl = { 49 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, 50 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, 51 .gp = IMX_GPIO_NR(4, 8), 52 }, 53 .sda = { 54 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, 55 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, 56 .gp = IMX_GPIO_NR(4, 9), 57 }, 58 }; 59 #endif 60 61 int dram_init(void) 62 { 63 gd->ram_size = PHYS_SDRAM_SIZE; 64 65 return 0; 66 } 67 68 static iomux_v3_cfg_t const wdog_pads[] = { 69 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 70 }; 71 72 static iomux_v3_cfg_t const uart1_pads[] = { 73 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 74 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 75 }; 76 77 static iomux_v3_cfg_t const usdhc1_pads[] = { 78 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 82 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 83 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 85 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 }; 88 89 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { 90 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 94 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 95 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 96 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 97 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 98 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 99 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 100 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 102 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 103 }; 104 105 #define IOX_SDI IMX_GPIO_NR(1, 9) 106 #define IOX_STCP IMX_GPIO_NR(1, 12) 107 #define IOX_SHCP IMX_GPIO_NR(1, 13) 108 109 static iomux_v3_cfg_t const iox_pads[] = { 110 /* IOX_SDI */ 111 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), 112 /* IOX_STCP */ 113 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 114 /* IOX_SHCP */ 115 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), 116 }; 117 118 /* 119 * PCIE_DIS_B --> Q0 120 * PCIE_RST_B --> Q1 121 * HDMI_RST_B --> Q2 122 * PERI_RST_B --> Q3 123 * SENSOR_RST_B --> Q4 124 * ENET_RST_B --> Q5 125 * PERI_3V3_EN --> Q6 126 * LCD_PWR_EN --> Q7 127 */ 128 enum qn { 129 PCIE_DIS_B, 130 PCIE_RST_B, 131 HDMI_RST_B, 132 PERI_RST_B, 133 SENSOR_RST_B, 134 ENET_RST_B, 135 PERI_3V3_EN, 136 LCD_PWR_EN, 137 }; 138 139 enum qn_func { 140 qn_reset, 141 qn_enable, 142 qn_disable, 143 }; 144 145 enum qn_level { 146 qn_low = 0, 147 qn_high = 1, 148 }; 149 150 static enum qn_level seq[3][2] = { 151 {0, 1}, {1, 1}, {0, 0} 152 }; 153 154 static enum qn_func qn_output[8] = { 155 qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, 156 qn_enable 157 }; 158 159 void iox74lv_init(void) 160 { 161 int i; 162 163 for (i = 7; i >= 0; i--) { 164 gpio_direction_output(IOX_SHCP, 0); 165 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 166 udelay(500); 167 gpio_direction_output(IOX_SHCP, 1); 168 udelay(500); 169 } 170 171 gpio_direction_output(IOX_STCP, 0); 172 udelay(500); 173 /* 174 * shift register will be output to pins 175 */ 176 gpio_direction_output(IOX_STCP, 1); 177 178 for (i = 7; i >= 0; i--) { 179 gpio_direction_output(IOX_SHCP, 0); 180 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 181 udelay(500); 182 gpio_direction_output(IOX_SHCP, 1); 183 udelay(500); 184 } 185 gpio_direction_output(IOX_STCP, 0); 186 udelay(500); 187 /* 188 * shift register will be output to pins 189 */ 190 gpio_direction_output(IOX_STCP, 1); 191 }; 192 193 void iox74lv_set(int index) 194 { 195 int i; 196 for (i = 7; i >= 0; i--) { 197 gpio_direction_output(IOX_SHCP, 0); 198 199 if (i == index) 200 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 201 else 202 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 203 udelay(500); 204 gpio_direction_output(IOX_SHCP, 1); 205 udelay(500); 206 } 207 208 gpio_direction_output(IOX_STCP, 0); 209 udelay(500); 210 /* 211 * shift register will be output to pins 212 */ 213 gpio_direction_output(IOX_STCP, 1); 214 215 for (i = 7; i >= 0; i--) { 216 gpio_direction_output(IOX_SHCP, 0); 217 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 218 udelay(500); 219 gpio_direction_output(IOX_SHCP, 1); 220 udelay(500); 221 } 222 223 gpio_direction_output(IOX_STCP, 0); 224 udelay(500); 225 /* 226 * shift register will be output to pins 227 */ 228 gpio_direction_output(IOX_STCP, 1); 229 }; 230 231 #ifdef CONFIG_FEC_MXC 232 static iomux_v3_cfg_t const fec1_pads[] = { 233 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 234 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 235 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 236 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 237 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 238 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 239 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 240 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 241 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 242 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 243 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 244 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 245 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 246 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 247 }; 248 249 static void setup_iomux_fec(void) 250 { 251 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 252 } 253 #endif 254 255 static void setup_iomux_uart(void) 256 { 257 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 258 } 259 260 #ifdef CONFIG_FSL_ESDHC 261 262 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) 263 #define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) 264 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) 265 266 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 267 {USDHC1_BASE_ADDR, 0, 4}, 268 {USDHC3_BASE_ADDR}, 269 }; 270 271 static int mmc_get_env_devno(void) 272 { 273 struct bootrom_sw_info **p = 274 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; 275 276 u8 boot_type = (*p)->boot_dev_type; 277 u8 dev_no = (*p)->boot_dev_instance; 278 279 /* If not boot from sd/mmc, use default value */ 280 if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) 281 return CONFIG_SYS_MMC_ENV_DEV; 282 283 if (dev_no == 2) 284 dev_no--; 285 286 return dev_no; 287 } 288 289 static int mmc_map_to_kernel_blk(int dev_no) 290 { 291 if (dev_no == 1) 292 dev_no++; 293 294 return dev_no; 295 } 296 297 int board_mmc_getcd(struct mmc *mmc) 298 { 299 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 300 int ret = 0; 301 302 switch (cfg->esdhc_base) { 303 case USDHC1_BASE_ADDR: 304 ret = !gpio_get_value(USDHC1_CD_GPIO); 305 break; 306 case USDHC3_BASE_ADDR: 307 ret = 1; /* Assume uSDHC3 emmc is always present */ 308 break; 309 } 310 311 return ret; 312 } 313 314 int board_mmc_init(bd_t *bis) 315 { 316 int i, ret; 317 /* 318 * According to the board_mmc_init() the following map is done: 319 * (U-boot device node) (Physical Port) 320 * mmc0 USDHC1 321 * mmc2 USDHC3 (eMMC) 322 */ 323 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 324 switch (i) { 325 case 0: 326 imx_iomux_v3_setup_multiple_pads( 327 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 328 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 329 gpio_direction_input(USDHC1_CD_GPIO); 330 gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); 331 gpio_direction_output(USDHC1_PWR_GPIO, 0); 332 udelay(500); 333 gpio_direction_output(USDHC1_PWR_GPIO, 1); 334 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 335 break; 336 case 1: 337 imx_iomux_v3_setup_multiple_pads( 338 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); 339 gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); 340 gpio_direction_output(USDHC3_PWR_GPIO, 0); 341 udelay(500); 342 gpio_direction_output(USDHC3_PWR_GPIO, 1); 343 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 344 break; 345 default: 346 printf("Warning: you configured more USDHC controllers" 347 "(%d) than supported by the board\n", i + 1); 348 return -EINVAL; 349 } 350 351 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 352 if (ret) 353 return ret; 354 } 355 356 return 0; 357 } 358 359 static int check_mmc_autodetect(void) 360 { 361 char *autodetect_str = getenv("mmcautodetect"); 362 363 if ((autodetect_str != NULL) && 364 (strcmp(autodetect_str, "yes") == 0)) { 365 return 1; 366 } 367 368 return 0; 369 } 370 371 static void mmc_late_init(void) 372 { 373 char cmd[32]; 374 char mmcblk[32]; 375 u32 dev_no = mmc_get_env_devno(); 376 377 if (!check_mmc_autodetect()) 378 return; 379 380 setenv_ulong("mmcdev", dev_no); 381 382 /* Set mmcblk env */ 383 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", 384 mmc_map_to_kernel_blk(dev_no)); 385 setenv("mmcroot", mmcblk); 386 387 sprintf(cmd, "mmc dev %d", dev_no); 388 run_command(cmd, 0); 389 } 390 391 #endif 392 393 #ifdef CONFIG_FEC_MXC 394 int board_eth_init(bd_t *bis) 395 { 396 int ret; 397 398 setup_iomux_fec(); 399 400 ret = fecmxc_initialize_multi(bis, 0, 401 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 402 if (ret) 403 printf("FEC1 MXC: %s:failed\n", __func__); 404 405 return ret; 406 } 407 408 static int setup_fec(void) 409 { 410 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 411 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 412 413 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ 414 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 415 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | 416 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); 417 418 return set_clk_enet(ENET_125MHz); 419 } 420 421 422 int board_phy_config(struct phy_device *phydev) 423 { 424 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 425 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); 426 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); 427 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); 428 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); 429 430 if (phydev->drv->config) 431 phydev->drv->config(phydev); 432 return 0; 433 } 434 #endif 435 436 int board_early_init_f(void) 437 { 438 setup_iomux_uart(); 439 440 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 441 442 return 0; 443 } 444 445 int board_init(void) 446 { 447 /* address of boot parameters */ 448 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 449 450 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 451 452 iox74lv_init(); 453 454 #ifdef CONFIG_FEC_MXC 455 setup_fec(); 456 #endif 457 458 return 0; 459 } 460 461 #ifdef CONFIG_CMD_BMODE 462 static const struct boot_mode board_boot_modes[] = { 463 /* 4 bit bus width */ 464 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, 465 {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, 466 {NULL, 0}, 467 }; 468 #endif 469 470 #ifdef CONFIG_POWER 471 #define I2C_PMIC 0 472 int power_init_board(void) 473 { 474 struct pmic *p; 475 int ret; 476 unsigned int reg, rev_id; 477 478 ret = power_pfuze3000_init(I2C_PMIC); 479 if (ret) 480 return ret; 481 482 p = pmic_get("PFUZE3000"); 483 ret = pmic_probe(p); 484 if (ret) 485 return ret; 486 487 pmic_reg_read(p, PFUZE3000_DEVICEID, ®); 488 pmic_reg_read(p, PFUZE3000_REVID, &rev_id); 489 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); 490 491 /* disable Low Power Mode during standby mode */ 492 pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); 493 reg |= 0x1; 494 pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); 495 496 return 0; 497 } 498 #endif 499 500 int board_late_init(void) 501 { 502 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 503 504 #ifdef CONFIG_CMD_BMODE 505 add_board_boot_modes(board_boot_modes); 506 #endif 507 508 #ifdef CONFIG_ENV_IS_IN_MMC 509 mmc_late_init(); 510 #endif 511 512 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 513 514 set_wdog_reset(wdog); 515 516 /* 517 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), 518 * since we use PMIC_PWRON to reset the board. 519 */ 520 clrsetbits_le16(&wdog->wcr, 0, 0x10); 521 522 return 0; 523 } 524 525 u32 get_board_rev(void) 526 { 527 return get_cpu_rev(); 528 } 529 530 int checkboard(void) 531 { 532 puts("Board: i.MX7D SABRESD\n"); 533 534 return 0; 535 } 536 537 #ifdef CONFIG_USB_EHCI_MX7 538 iomux_v3_cfg_t const usb_otg1_pads[] = { 539 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 540 }; 541 542 iomux_v3_cfg_t const usb_otg2_pads[] = { 543 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 544 }; 545 546 int board_ehci_hcd_init(int port) 547 { 548 switch (port) { 549 case 0: 550 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, 551 ARRAY_SIZE(usb_otg1_pads)); 552 break; 553 case 1: 554 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 555 ARRAY_SIZE(usb_otg2_pads)); 556 break; 557 default: 558 printf("MXC USB port %d not yet supported\n", port); 559 return -EINVAL; 560 } 561 return 0; 562 } 563 #endif 564