1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/mx7-pins.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/gpio.h> 12 #include <asm/imx-common/iomux-v3.h> 13 #include <asm/imx-common/boot_mode.h> 14 #include <asm/io.h> 15 #include <linux/sizes.h> 16 #include <common.h> 17 #include <fsl_esdhc.h> 18 #include <mmc.h> 19 #include <miiphy.h> 20 #include <netdev.h> 21 #include <power/pmic.h> 22 #include <power/pfuze3000_pmic.h> 23 #include "../common/pfuze.h" 24 #include <i2c.h> 25 #include <asm/imx-common/mxc_i2c.h> 26 #include <asm/arch/crm_regs.h> 27 #include <usb/ehci-fsl.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 32 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 33 34 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 35 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 36 37 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 38 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 39 40 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 41 42 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 43 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) 44 45 #ifdef CONFIG_SYS_I2C_MXC 46 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 47 /* I2C1 for PMIC */ 48 static struct i2c_pads_info i2c_pad_info1 = { 49 .scl = { 50 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, 51 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, 52 .gp = IMX_GPIO_NR(4, 8), 53 }, 54 .sda = { 55 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, 56 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, 57 .gp = IMX_GPIO_NR(4, 9), 58 }, 59 }; 60 #endif 61 62 int dram_init(void) 63 { 64 gd->ram_size = PHYS_SDRAM_SIZE; 65 66 return 0; 67 } 68 69 static iomux_v3_cfg_t const wdog_pads[] = { 70 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 71 }; 72 73 static iomux_v3_cfg_t const uart1_pads[] = { 74 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 75 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 76 }; 77 78 static iomux_v3_cfg_t const usdhc1_pads[] = { 79 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 82 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 83 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 86 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 }; 89 90 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { 91 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 94 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 95 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 96 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 97 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 98 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 99 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 100 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), 102 103 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 }; 105 106 #define IOX_SDI IMX_GPIO_NR(1, 9) 107 #define IOX_STCP IMX_GPIO_NR(1, 12) 108 #define IOX_SHCP IMX_GPIO_NR(1, 13) 109 110 static iomux_v3_cfg_t const iox_pads[] = { 111 /* IOX_SDI */ 112 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), 113 /* IOX_STCP */ 114 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 115 /* IOX_SHCP */ 116 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), 117 }; 118 119 /* 120 * PCIE_DIS_B --> Q0 121 * PCIE_RST_B --> Q1 122 * HDMI_RST_B --> Q2 123 * PERI_RST_B --> Q3 124 * SENSOR_RST_B --> Q4 125 * ENET_RST_B --> Q5 126 * PERI_3V3_EN --> Q6 127 * LCD_PWR_EN --> Q7 128 */ 129 enum qn { 130 PCIE_DIS_B, 131 PCIE_RST_B, 132 HDMI_RST_B, 133 PERI_RST_B, 134 SENSOR_RST_B, 135 ENET_RST_B, 136 PERI_3V3_EN, 137 LCD_PWR_EN, 138 }; 139 140 enum qn_func { 141 qn_reset, 142 qn_enable, 143 qn_disable, 144 }; 145 146 enum qn_level { 147 qn_low = 0, 148 qn_high = 1, 149 }; 150 151 static enum qn_level seq[3][2] = { 152 {0, 1}, {1, 1}, {0, 0} 153 }; 154 155 static enum qn_func qn_output[8] = { 156 qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, 157 qn_enable 158 }; 159 160 static void iox74lv_init(void) 161 { 162 int i; 163 164 for (i = 7; i >= 0; i--) { 165 gpio_direction_output(IOX_SHCP, 0); 166 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 167 udelay(500); 168 gpio_direction_output(IOX_SHCP, 1); 169 udelay(500); 170 } 171 172 gpio_direction_output(IOX_STCP, 0); 173 udelay(500); 174 /* 175 * shift register will be output to pins 176 */ 177 gpio_direction_output(IOX_STCP, 1); 178 179 for (i = 7; i >= 0; i--) { 180 gpio_direction_output(IOX_SHCP, 0); 181 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 182 udelay(500); 183 gpio_direction_output(IOX_SHCP, 1); 184 udelay(500); 185 } 186 gpio_direction_output(IOX_STCP, 0); 187 udelay(500); 188 /* 189 * shift register will be output to pins 190 */ 191 gpio_direction_output(IOX_STCP, 1); 192 }; 193 194 #ifdef CONFIG_FEC_MXC 195 static iomux_v3_cfg_t const fec1_pads[] = { 196 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 197 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 198 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 199 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 200 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 201 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 202 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 203 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 204 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 205 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 206 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 207 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 208 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 209 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 210 }; 211 212 static void setup_iomux_fec(void) 213 { 214 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 215 } 216 #endif 217 218 static void setup_iomux_uart(void) 219 { 220 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 221 } 222 223 #ifdef CONFIG_FSL_ESDHC 224 225 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) 226 #define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) 227 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) 228 229 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 230 {USDHC1_BASE_ADDR, 0, 4}, 231 {USDHC3_BASE_ADDR}, 232 }; 233 234 static int mmc_get_env_devno(void) 235 { 236 struct bootrom_sw_info **p = 237 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; 238 239 u8 boot_type = (*p)->boot_dev_type; 240 u8 dev_no = (*p)->boot_dev_instance; 241 242 /* If not boot from sd/mmc, use default value */ 243 if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) 244 return CONFIG_SYS_MMC_ENV_DEV; 245 246 if (dev_no == 2) 247 dev_no--; 248 249 return dev_no; 250 } 251 252 static int mmc_map_to_kernel_blk(int dev_no) 253 { 254 if (dev_no == 1) 255 dev_no++; 256 257 return dev_no; 258 } 259 260 int board_mmc_getcd(struct mmc *mmc) 261 { 262 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 263 int ret = 0; 264 265 switch (cfg->esdhc_base) { 266 case USDHC1_BASE_ADDR: 267 ret = !gpio_get_value(USDHC1_CD_GPIO); 268 break; 269 case USDHC3_BASE_ADDR: 270 ret = 1; /* Assume uSDHC3 emmc is always present */ 271 break; 272 } 273 274 return ret; 275 } 276 277 int board_mmc_init(bd_t *bis) 278 { 279 int i, ret; 280 /* 281 * According to the board_mmc_init() the following map is done: 282 * (U-boot device node) (Physical Port) 283 * mmc0 USDHC1 284 * mmc2 USDHC3 (eMMC) 285 */ 286 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 287 switch (i) { 288 case 0: 289 imx_iomux_v3_setup_multiple_pads( 290 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 291 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 292 gpio_direction_input(USDHC1_CD_GPIO); 293 gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); 294 gpio_direction_output(USDHC1_PWR_GPIO, 0); 295 udelay(500); 296 gpio_direction_output(USDHC1_PWR_GPIO, 1); 297 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 298 break; 299 case 1: 300 imx_iomux_v3_setup_multiple_pads( 301 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); 302 gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); 303 gpio_direction_output(USDHC3_PWR_GPIO, 0); 304 udelay(500); 305 gpio_direction_output(USDHC3_PWR_GPIO, 1); 306 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 307 break; 308 default: 309 printf("Warning: you configured more USDHC controllers" 310 "(%d) than supported by the board\n", i + 1); 311 return -EINVAL; 312 } 313 314 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 315 if (ret) 316 return ret; 317 } 318 319 return 0; 320 } 321 322 static int check_mmc_autodetect(void) 323 { 324 char *autodetect_str = getenv("mmcautodetect"); 325 326 if ((autodetect_str != NULL) && 327 (strcmp(autodetect_str, "yes") == 0)) { 328 return 1; 329 } 330 331 return 0; 332 } 333 334 static void mmc_late_init(void) 335 { 336 char cmd[32]; 337 char mmcblk[32]; 338 u32 dev_no = mmc_get_env_devno(); 339 340 if (!check_mmc_autodetect()) 341 return; 342 343 setenv_ulong("mmcdev", dev_no); 344 345 /* Set mmcblk env */ 346 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", 347 mmc_map_to_kernel_blk(dev_no)); 348 setenv("mmcroot", mmcblk); 349 350 sprintf(cmd, "mmc dev %d", dev_no); 351 run_command(cmd, 0); 352 } 353 354 #endif 355 356 #ifdef CONFIG_FEC_MXC 357 int board_eth_init(bd_t *bis) 358 { 359 int ret; 360 361 setup_iomux_fec(); 362 363 ret = fecmxc_initialize_multi(bis, 0, 364 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 365 if (ret) 366 printf("FEC1 MXC: %s:failed\n", __func__); 367 368 return ret; 369 } 370 371 static int setup_fec(void) 372 { 373 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 374 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 375 376 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ 377 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 378 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | 379 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); 380 381 return set_clk_enet(ENET_125MHz); 382 } 383 384 385 int board_phy_config(struct phy_device *phydev) 386 { 387 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 388 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); 389 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); 390 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); 391 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); 392 393 if (phydev->drv->config) 394 phydev->drv->config(phydev); 395 return 0; 396 } 397 #endif 398 399 int board_early_init_f(void) 400 { 401 setup_iomux_uart(); 402 403 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 404 405 return 0; 406 } 407 408 int board_init(void) 409 { 410 /* address of boot parameters */ 411 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 412 413 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 414 415 iox74lv_init(); 416 417 #ifdef CONFIG_FEC_MXC 418 setup_fec(); 419 #endif 420 421 return 0; 422 } 423 424 #ifdef CONFIG_CMD_BMODE 425 static const struct boot_mode board_boot_modes[] = { 426 /* 4 bit bus width */ 427 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, 428 {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, 429 {NULL, 0}, 430 }; 431 #endif 432 433 #ifdef CONFIG_POWER 434 #define I2C_PMIC 0 435 int power_init_board(void) 436 { 437 struct pmic *p; 438 int ret; 439 unsigned int reg, rev_id; 440 441 ret = power_pfuze3000_init(I2C_PMIC); 442 if (ret) 443 return ret; 444 445 p = pmic_get("PFUZE3000"); 446 ret = pmic_probe(p); 447 if (ret) 448 return ret; 449 450 pmic_reg_read(p, PFUZE3000_DEVICEID, ®); 451 pmic_reg_read(p, PFUZE3000_REVID, &rev_id); 452 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); 453 454 /* disable Low Power Mode during standby mode */ 455 pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); 456 reg |= 0x1; 457 pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); 458 459 return 0; 460 } 461 #endif 462 463 int board_late_init(void) 464 { 465 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 466 467 #ifdef CONFIG_CMD_BMODE 468 add_board_boot_modes(board_boot_modes); 469 #endif 470 471 #ifdef CONFIG_ENV_IS_IN_MMC 472 mmc_late_init(); 473 #endif 474 475 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 476 477 set_wdog_reset(wdog); 478 479 /* 480 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), 481 * since we use PMIC_PWRON to reset the board. 482 */ 483 clrsetbits_le16(&wdog->wcr, 0, 0x10); 484 485 return 0; 486 } 487 488 u32 get_board_rev(void) 489 { 490 return get_cpu_rev(); 491 } 492 493 int checkboard(void) 494 { 495 puts("Board: i.MX7D SABRESD\n"); 496 497 return 0; 498 } 499 500 #ifdef CONFIG_USB_EHCI_MX7 501 static iomux_v3_cfg_t const usb_otg1_pads[] = { 502 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 503 }; 504 505 static iomux_v3_cfg_t const usb_otg2_pads[] = { 506 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 507 }; 508 509 int board_ehci_hcd_init(int port) 510 { 511 switch (port) { 512 case 0: 513 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, 514 ARRAY_SIZE(usb_otg1_pads)); 515 break; 516 case 1: 517 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 518 ARRAY_SIZE(usb_otg2_pads)); 519 break; 520 default: 521 printf("MXC USB port %d not yet supported\n", port); 522 return -EINVAL; 523 } 524 return 0; 525 } 526 #endif 527