1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/iomux.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/mx6ul_pins.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/gpio.h> 15 #include <asm/mach-imx/iomux-v3.h> 16 #include <asm/mach-imx/boot_mode.h> 17 #include <asm/mach-imx/mxc_i2c.h> 18 #include <asm/io.h> 19 #include <common.h> 20 #include <fsl_esdhc.h> 21 #include <i2c.h> 22 #include <miiphy.h> 23 #include <linux/sizes.h> 24 #include <mmc.h> 25 #include <netdev.h> 26 #include <power/pmic.h> 27 #include <power/pfuze3000_pmic.h> 28 #include "../common/pfuze.h" 29 #include <usb.h> 30 #include <usb/ehci-ci.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 37 38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 41 42 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 43 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ 44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 45 46 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 49 PAD_CTL_ODE) 50 51 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 52 PAD_CTL_SPEED_HIGH | \ 53 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 54 55 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 56 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) 57 58 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 59 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) 60 61 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 62 63 #define IOX_SDI IMX_GPIO_NR(5, 10) 64 #define IOX_STCP IMX_GPIO_NR(5, 7) 65 #define IOX_SHCP IMX_GPIO_NR(5, 11) 66 #define IOX_OE IMX_GPIO_NR(5, 8) 67 68 static iomux_v3_cfg_t const iox_pads[] = { 69 /* IOX_SDI */ 70 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 71 /* IOX_SHCP */ 72 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 73 /* IOX_STCP */ 74 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 75 /* IOX_nOE */ 76 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 77 }; 78 79 /* 80 * HDMI_nRST --> Q0 81 * ENET1_nRST --> Q1 82 * ENET2_nRST --> Q2 83 * CAN1_2_STBY --> Q3 84 * BT_nPWD --> Q4 85 * CSI_RST --> Q5 86 * CSI_PWDN --> Q6 87 * LCD_nPWREN --> Q7 88 */ 89 enum qn { 90 HDMI_NRST, 91 ENET1_NRST, 92 ENET2_NRST, 93 CAN1_2_STBY, 94 BT_NPWD, 95 CSI_RST, 96 CSI_PWDN, 97 LCD_NPWREN, 98 }; 99 100 enum qn_func { 101 qn_reset, 102 qn_enable, 103 qn_disable, 104 }; 105 106 enum qn_level { 107 qn_low = 0, 108 qn_high = 1, 109 }; 110 111 static enum qn_level seq[3][2] = { 112 {0, 1}, {1, 1}, {0, 0} 113 }; 114 115 static enum qn_func qn_output[8] = { 116 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, 117 qn_disable, qn_disable 118 }; 119 120 static void iox74lv_init(void) 121 { 122 int i; 123 124 gpio_direction_output(IOX_OE, 0); 125 126 for (i = 7; i >= 0; i--) { 127 gpio_direction_output(IOX_SHCP, 0); 128 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 129 udelay(500); 130 gpio_direction_output(IOX_SHCP, 1); 131 udelay(500); 132 } 133 134 gpio_direction_output(IOX_STCP, 0); 135 udelay(500); 136 /* 137 * shift register will be output to pins 138 */ 139 gpio_direction_output(IOX_STCP, 1); 140 141 for (i = 7; i >= 0; i--) { 142 gpio_direction_output(IOX_SHCP, 0); 143 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 144 udelay(500); 145 gpio_direction_output(IOX_SHCP, 1); 146 udelay(500); 147 } 148 gpio_direction_output(IOX_STCP, 0); 149 udelay(500); 150 /* 151 * shift register will be output to pins 152 */ 153 gpio_direction_output(IOX_STCP, 1); 154 }; 155 156 #ifdef CONFIG_SYS_I2C_MXC 157 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 158 /* I2C1 for PMIC and EEPROM */ 159 static struct i2c_pads_info i2c_pad_info1 = { 160 .scl = { 161 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, 162 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, 163 .gp = IMX_GPIO_NR(1, 28), 164 }, 165 .sda = { 166 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, 167 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, 168 .gp = IMX_GPIO_NR(1, 29), 169 }, 170 }; 171 172 #ifdef CONFIG_POWER 173 #define I2C_PMIC 0 174 int power_init_board(void) 175 { 176 if (is_mx6ul_9x9_evk()) { 177 struct pmic *pfuze; 178 int ret; 179 unsigned int reg, rev_id; 180 181 ret = power_pfuze3000_init(I2C_PMIC); 182 if (ret) 183 return ret; 184 185 pfuze = pmic_get("PFUZE3000"); 186 ret = pmic_probe(pfuze); 187 if (ret) 188 return ret; 189 190 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); 191 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); 192 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", 193 reg, rev_id); 194 195 /* disable Low Power Mode during standby mode */ 196 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); 197 198 /* SW1B step ramp up time from 2us to 4us/25mV */ 199 reg = 0x40; 200 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); 201 202 /* SW1B mode to APS/PFM */ 203 reg = 0xc; 204 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); 205 206 /* SW1B standby voltage set to 0.975V */ 207 reg = 0xb; 208 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); 209 } 210 211 return 0; 212 } 213 #endif 214 #endif 215 216 int dram_init(void) 217 { 218 gd->ram_size = imx_ddr_size(); 219 220 return 0; 221 } 222 223 static iomux_v3_cfg_t const uart1_pads[] = { 224 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 225 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 226 }; 227 228 #ifndef CONFIG_SPL_BUILD 229 static iomux_v3_cfg_t const usdhc1_pads[] = { 230 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 231 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 232 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 233 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 234 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 235 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 236 237 /* VSELECT */ 238 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), 239 /* CD */ 240 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 241 /* RST_B */ 242 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 243 }; 244 #endif 245 246 /* 247 * mx6ul_14x14_evk board default supports sd card. If want to use 248 * EMMC, need to do board rework for sd2. 249 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support 250 * emmc, need to define this macro. 251 */ 252 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 253 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { 254 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 255 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 256 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 257 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 258 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 259 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 260 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 261 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 262 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 263 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 264 265 /* 266 * RST_B 267 */ 268 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 269 }; 270 #else 271 static iomux_v3_cfg_t const usdhc2_pads[] = { 272 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 273 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 274 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 275 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 276 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 277 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 278 }; 279 280 /* 281 * The evk board uses DAT3 to detect CD card plugin, 282 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. 283 */ 284 static iomux_v3_cfg_t const usdhc2_cd_pad = 285 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL); 286 287 static iomux_v3_cfg_t const usdhc2_dat3_pad = 288 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | 289 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL); 290 #endif 291 292 static void setup_iomux_uart(void) 293 { 294 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 295 } 296 297 #ifdef CONFIG_FSL_QSPI 298 299 #define QSPI_PAD_CTRL1 \ 300 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ 301 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) 302 303 static iomux_v3_cfg_t const quadspi_pads[] = { 304 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 305 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 306 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 307 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 308 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 309 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 310 }; 311 312 static int board_qspi_init(void) 313 { 314 /* Set the iomux */ 315 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 316 ARRAY_SIZE(quadspi_pads)); 317 /* Set the clock */ 318 enable_qspi_clk(0); 319 320 return 0; 321 } 322 #endif 323 324 #ifdef CONFIG_FSL_ESDHC 325 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 326 {USDHC1_BASE_ADDR, 0, 4}, 327 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 328 {USDHC2_BASE_ADDR, 0, 8}, 329 #else 330 {USDHC2_BASE_ADDR, 0, 4}, 331 #endif 332 }; 333 334 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) 335 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) 336 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) 337 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) 338 339 int board_mmc_getcd(struct mmc *mmc) 340 { 341 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 342 int ret = 0; 343 344 switch (cfg->esdhc_base) { 345 case USDHC1_BASE_ADDR: 346 ret = !gpio_get_value(USDHC1_CD_GPIO); 347 break; 348 case USDHC2_BASE_ADDR: 349 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 350 ret = 1; 351 #else 352 imx_iomux_v3_setup_pad(usdhc2_cd_pad); 353 gpio_direction_input(USDHC2_CD_GPIO); 354 355 /* 356 * Since it is the DAT3 pin, this pin is pulled to 357 * low voltage if no card 358 */ 359 ret = gpio_get_value(USDHC2_CD_GPIO); 360 361 imx_iomux_v3_setup_pad(usdhc2_dat3_pad); 362 #endif 363 break; 364 } 365 366 return ret; 367 } 368 369 int board_mmc_init(bd_t *bis) 370 { 371 #ifdef CONFIG_SPL_BUILD 372 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 373 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, 374 ARRAY_SIZE(usdhc2_emmc_pads)); 375 #else 376 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 377 #endif 378 gpio_direction_output(USDHC2_PWR_GPIO, 0); 379 udelay(500); 380 gpio_direction_output(USDHC2_PWR_GPIO, 1); 381 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 382 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); 383 #else 384 int i, ret; 385 386 /* 387 * According to the board_mmc_init() the following map is done: 388 * (U-Boot device node) (Physical Port) 389 * mmc0 USDHC1 390 * mmc1 USDHC2 391 */ 392 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 393 switch (i) { 394 case 0: 395 imx_iomux_v3_setup_multiple_pads( 396 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 397 gpio_direction_input(USDHC1_CD_GPIO); 398 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 399 400 gpio_direction_output(USDHC1_PWR_GPIO, 0); 401 udelay(500); 402 gpio_direction_output(USDHC1_PWR_GPIO, 1); 403 break; 404 case 1: 405 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 406 imx_iomux_v3_setup_multiple_pads( 407 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); 408 #else 409 imx_iomux_v3_setup_multiple_pads( 410 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 411 #endif 412 gpio_direction_output(USDHC2_PWR_GPIO, 0); 413 udelay(500); 414 gpio_direction_output(USDHC2_PWR_GPIO, 1); 415 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 416 break; 417 default: 418 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); 419 return -EINVAL; 420 } 421 422 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 423 if (ret) { 424 printf("Warning: failed to initialize mmc dev %d\n", i); 425 return ret; 426 } 427 } 428 #endif 429 return 0; 430 } 431 #endif 432 433 #ifdef CONFIG_USB_EHCI_MX6 434 #define USB_OTHERREGS_OFFSET 0x800 435 #define UCTRL_PWR_POL (1 << 9) 436 437 static iomux_v3_cfg_t const usb_otg_pads[] = { 438 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 439 }; 440 441 /* At default the 3v3 enables the MIC2026 for VBUS power */ 442 static void setup_usb(void) 443 { 444 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 445 ARRAY_SIZE(usb_otg_pads)); 446 } 447 448 int board_usb_phy_mode(int port) 449 { 450 if (port == 1) 451 return USB_INIT_HOST; 452 else 453 return usb_phy_mode(port); 454 } 455 456 int board_ehci_hcd_init(int port) 457 { 458 u32 *usbnc_usb_ctrl; 459 460 if (port > 1) 461 return -EINVAL; 462 463 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 464 port * 4); 465 466 /* Set Power polarity */ 467 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 468 469 return 0; 470 } 471 #endif 472 473 #ifdef CONFIG_FEC_MXC 474 /* 475 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only 476 * be used for ENET1 or ENET2, cannot be used for both. 477 */ 478 static iomux_v3_cfg_t const fec1_pads[] = { 479 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 480 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 481 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 482 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 483 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 484 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 485 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 486 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 487 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 488 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 489 }; 490 491 static iomux_v3_cfg_t const fec2_pads[] = { 492 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 493 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 494 495 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 496 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 497 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 498 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 499 500 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 501 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 502 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 503 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 504 }; 505 506 static void setup_iomux_fec(int fec_id) 507 { 508 if (fec_id == 0) 509 imx_iomux_v3_setup_multiple_pads(fec1_pads, 510 ARRAY_SIZE(fec1_pads)); 511 else 512 imx_iomux_v3_setup_multiple_pads(fec2_pads, 513 ARRAY_SIZE(fec2_pads)); 514 } 515 516 int board_eth_init(bd_t *bis) 517 { 518 setup_iomux_fec(CONFIG_FEC_ENET_DEV); 519 520 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, 521 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 522 } 523 524 static int setup_fec(int fec_id) 525 { 526 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 527 int ret; 528 529 if (fec_id == 0) { 530 /* 531 * Use 50M anatop loopback REF_CLK1 for ENET1, 532 * clear gpr1[13], set gpr1[17]. 533 */ 534 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 535 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); 536 } else { 537 /* 538 * Use 50M anatop loopback REF_CLK2 for ENET2, 539 * clear gpr1[14], set gpr1[18]. 540 */ 541 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 542 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); 543 } 544 545 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); 546 if (ret) 547 return ret; 548 549 enable_enet_clk(1); 550 551 return 0; 552 } 553 554 int board_phy_config(struct phy_device *phydev) 555 { 556 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); 557 558 if (phydev->drv->config) 559 phydev->drv->config(phydev); 560 561 return 0; 562 } 563 #endif 564 565 #ifdef CONFIG_VIDEO_MXS 566 static iomux_v3_cfg_t const lcd_pads[] = { 567 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 568 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 569 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 570 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 571 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), 572 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), 573 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), 574 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), 575 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), 576 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), 577 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), 578 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), 579 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), 580 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), 581 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 582 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 583 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 584 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 585 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 586 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 587 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 588 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 589 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 590 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 591 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 592 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 593 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 594 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 595 596 /* LCD_RST */ 597 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 598 599 /* Use GPIO for Brightness adjustment, duty cycle = period. */ 600 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 601 }; 602 603 static int setup_lcd(void) 604 { 605 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); 606 607 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 608 609 /* Reset the LCD */ 610 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); 611 udelay(500); 612 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); 613 614 /* Set Brightness to high */ 615 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); 616 617 return 0; 618 } 619 #endif 620 621 int board_early_init_f(void) 622 { 623 setup_iomux_uart(); 624 625 return 0; 626 } 627 628 int board_init(void) 629 { 630 /* Address of boot parameters */ 631 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 632 633 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 634 635 iox74lv_init(); 636 637 #ifdef CONFIG_SYS_I2C_MXC 638 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 639 #endif 640 641 #ifdef CONFIG_FEC_MXC 642 setup_fec(CONFIG_FEC_ENET_DEV); 643 #endif 644 645 #ifdef CONFIG_USB_EHCI_MX6 646 setup_usb(); 647 #endif 648 649 #ifdef CONFIG_FSL_QSPI 650 board_qspi_init(); 651 #endif 652 653 #ifdef CONFIG_VIDEO_MXS 654 setup_lcd(); 655 #endif 656 657 return 0; 658 } 659 660 #ifdef CONFIG_CMD_BMODE 661 static const struct boot_mode board_boot_modes[] = { 662 /* 4 bit bus width */ 663 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, 664 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 665 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, 666 {NULL, 0}, 667 }; 668 #endif 669 670 int board_late_init(void) 671 { 672 #ifdef CONFIG_CMD_BMODE 673 add_board_boot_modes(board_boot_modes); 674 #endif 675 676 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 677 env_set("board_name", "EVK"); 678 679 if (is_mx6ul_9x9_evk()) 680 env_set("board_rev", "9X9"); 681 else 682 env_set("board_rev", "14X14"); 683 #endif 684 685 return 0; 686 } 687 688 int checkboard(void) 689 { 690 if (is_mx6ul_9x9_evk()) 691 puts("Board: MX6UL 9x9 EVK\n"); 692 else 693 puts("Board: MX6UL 14x14 EVK\n"); 694 695 return 0; 696 } 697 698 #ifdef CONFIG_SPL_BUILD 699 #include <libfdt.h> 700 #include <spl.h> 701 #include <asm/arch/mx6-ddr.h> 702 703 704 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 705 .grp_addds = 0x00000030, 706 .grp_ddrmode_ctl = 0x00020000, 707 .grp_b0ds = 0x00000030, 708 .grp_ctlds = 0x00000030, 709 .grp_b1ds = 0x00000030, 710 .grp_ddrpke = 0x00000000, 711 .grp_ddrmode = 0x00020000, 712 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK 713 .grp_ddr_type = 0x00080000, 714 #else 715 .grp_ddr_type = 0x000c0000, 716 #endif 717 }; 718 719 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK 720 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 721 .dram_dqm0 = 0x00000030, 722 .dram_dqm1 = 0x00000030, 723 .dram_ras = 0x00000030, 724 .dram_cas = 0x00000030, 725 .dram_odt0 = 0x00000000, 726 .dram_odt1 = 0x00000000, 727 .dram_sdba2 = 0x00000000, 728 .dram_sdclk_0 = 0x00000030, 729 .dram_sdqs0 = 0x00003030, 730 .dram_sdqs1 = 0x00003030, 731 .dram_reset = 0x00000030, 732 }; 733 734 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 735 .p0_mpwldectrl0 = 0x00000000, 736 .p0_mpdgctrl0 = 0x20000000, 737 .p0_mprddlctl = 0x4040484f, 738 .p0_mpwrdlctl = 0x40405247, 739 .mpzqlp2ctl = 0x1b4700c7, 740 }; 741 742 static struct mx6_lpddr2_cfg mem_ddr = { 743 .mem_speed = 800, 744 .density = 2, 745 .width = 16, 746 .banks = 4, 747 .rowaddr = 14, 748 .coladdr = 10, 749 .trcd_lp = 1500, 750 .trppb_lp = 1500, 751 .trpab_lp = 2000, 752 .trasmin = 4250, 753 }; 754 755 struct mx6_ddr_sysinfo ddr_sysinfo = { 756 .dsize = 0, 757 .cs_density = 18, 758 .ncs = 1, 759 .cs1_mirror = 0, 760 .walat = 0, 761 .ralat = 5, 762 .mif3_mode = 3, 763 .bi_on = 1, 764 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ 765 .rtt_nom = 0, 766 .sde_to_rst = 0, /* LPDDR2 does not need this field */ 767 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ 768 .ddr_type = DDR_TYPE_LPDDR2, 769 .refsel = 0, /* Refresh cycles at 64KHz */ 770 .refr = 3, /* 4 refresh commands per refresh cycle */ 771 }; 772 773 #else 774 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 775 .dram_dqm0 = 0x00000030, 776 .dram_dqm1 = 0x00000030, 777 .dram_ras = 0x00000030, 778 .dram_cas = 0x00000030, 779 .dram_odt0 = 0x00000030, 780 .dram_odt1 = 0x00000030, 781 .dram_sdba2 = 0x00000000, 782 .dram_sdclk_0 = 0x00000030, 783 .dram_sdqs0 = 0x00000030, 784 .dram_sdqs1 = 0x00000030, 785 .dram_reset = 0x00000030, 786 }; 787 788 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 789 .p0_mpwldectrl0 = 0x00000000, 790 .p0_mpdgctrl0 = 0x41570155, 791 .p0_mprddlctl = 0x4040474A, 792 .p0_mpwrdlctl = 0x40405550, 793 }; 794 795 struct mx6_ddr_sysinfo ddr_sysinfo = { 796 .dsize = 0, 797 .cs_density = 20, 798 .ncs = 1, 799 .cs1_mirror = 0, 800 .rtt_wr = 2, 801 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 802 .walat = 0, /* Write additional latency */ 803 .ralat = 5, /* Read additional latency */ 804 .mif3_mode = 3, /* Command prediction working mode */ 805 .bi_on = 1, /* Bank interleaving enabled */ 806 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 807 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 808 .ddr_type = DDR_TYPE_DDR3, 809 .refsel = 0, /* Refresh cycles at 64KHz */ 810 .refr = 1, /* 2 refresh commands per refresh cycle */ 811 }; 812 813 static struct mx6_ddr3_cfg mem_ddr = { 814 .mem_speed = 800, 815 .density = 4, 816 .width = 16, 817 .banks = 8, 818 .rowaddr = 15, 819 .coladdr = 10, 820 .pagesz = 2, 821 .trcd = 1375, 822 .trcmin = 4875, 823 .trasmin = 3500, 824 }; 825 #endif 826 827 static void ccgr_init(void) 828 { 829 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 830 831 writel(0xFFFFFFFF, &ccm->CCGR0); 832 writel(0xFFFFFFFF, &ccm->CCGR1); 833 writel(0xFFFFFFFF, &ccm->CCGR2); 834 writel(0xFFFFFFFF, &ccm->CCGR3); 835 writel(0xFFFFFFFF, &ccm->CCGR4); 836 writel(0xFFFFFFFF, &ccm->CCGR5); 837 writel(0xFFFFFFFF, &ccm->CCGR6); 838 writel(0xFFFFFFFF, &ccm->CCGR7); 839 } 840 841 static void spl_dram_init(void) 842 { 843 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 844 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 845 } 846 847 void board_init_f(ulong dummy) 848 { 849 ccgr_init(); 850 851 /* setup AIPS and disable watchdog */ 852 arch_cpu_init(); 853 854 /* iomux and setup of i2c */ 855 board_early_init_f(); 856 857 /* setup GP timer */ 858 timer_init(); 859 860 /* UART clocks enabled and gd valid - init serial console */ 861 preloader_console_init(); 862 863 /* DDR initialization */ 864 spl_dram_init(); 865 866 /* Clear the BSS. */ 867 memset(__bss_start, 0, __bss_end - __bss_start); 868 869 /* load/boot image from boot device */ 870 board_init_r(NULL, 0); 871 } 872 #endif 873