1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #include <asm/arch/clock.h> 7 #include <asm/arch/iomux.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/crm_regs.h> 10 #include <asm/arch/mx6ul_pins.h> 11 #include <asm/arch/mx6-pins.h> 12 #include <asm/arch/sys_proto.h> 13 #include <asm/gpio.h> 14 #include <asm/mach-imx/iomux-v3.h> 15 #include <asm/mach-imx/boot_mode.h> 16 #include <asm/mach-imx/mxc_i2c.h> 17 #include <asm/io.h> 18 #include <common.h> 19 #include <fsl_esdhc.h> 20 #include <i2c.h> 21 #include <miiphy.h> 22 #include <linux/sizes.h> 23 #include <mmc.h> 24 #include <netdev.h> 25 #include <power/pmic.h> 26 #include <power/pfuze3000_pmic.h> 27 #include "../common/pfuze.h" 28 #include <usb.h> 29 #include <usb/ehci-ci.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 34 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 35 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 36 37 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 38 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 39 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 40 41 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 42 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ 43 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 44 45 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 46 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 47 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 48 PAD_CTL_ODE) 49 50 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 51 PAD_CTL_SPEED_HIGH | \ 52 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 53 54 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 55 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) 56 57 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 58 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) 59 60 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 61 62 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 63 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 64 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 65 66 #ifdef CONFIG_DM_PMIC 67 int power_init_board(void) 68 { 69 struct udevice *dev; 70 int ret, dev_id, rev_id; 71 unsigned int reg; 72 73 ret = pmic_get("pfuze3000", &dev); 74 if (ret == -ENODEV) 75 return 0; 76 if (ret != 0) 77 return ret; 78 79 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); 80 rev_id = pmic_reg_read(dev, PFUZE3000_REVID); 81 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); 82 83 /* disable Low Power Mode during standby mode */ 84 reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); 85 reg |= 0x1; 86 pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); 87 88 /* SW1B step ramp up time from 2us to 4us/25mV */ 89 reg = 0x40; 90 pmic_reg_write(dev, PFUZE3000_SW1BCONF, reg); 91 92 /* SW1B mode to APS/PFM */ 93 reg = 0xc; 94 pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); 95 96 /* SW1B standby voltage set to 0.975V */ 97 reg = 0xb; 98 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); 99 100 return 0; 101 } 102 #endif 103 104 int dram_init(void) 105 { 106 gd->ram_size = imx_ddr_size(); 107 108 return 0; 109 } 110 111 static iomux_v3_cfg_t const uart1_pads[] = { 112 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 113 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 114 }; 115 116 #ifndef CONFIG_SPL_BUILD 117 static iomux_v3_cfg_t const usdhc1_pads[] = { 118 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 119 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 120 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 121 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 122 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 123 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 125 /* VSELECT */ 126 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), 127 /* CD */ 128 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 129 /* RST_B */ 130 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 131 }; 132 #endif 133 134 /* 135 * mx6ul_14x14_evk board default supports sd card. If want to use 136 * EMMC, need to do board rework for sd2. 137 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support 138 * emmc, need to define this macro. 139 */ 140 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 141 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { 142 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 144 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 145 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 146 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 147 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 148 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 149 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 150 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 151 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152 153 /* 154 * RST_B 155 */ 156 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 157 }; 158 #else 159 static iomux_v3_cfg_t const usdhc2_pads[] = { 160 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 161 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 162 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 163 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 164 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 165 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 166 }; 167 168 /* 169 * The evk board uses DAT3 to detect CD card plugin, 170 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. 171 */ 172 static iomux_v3_cfg_t const usdhc2_cd_pad = 173 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL); 174 175 static iomux_v3_cfg_t const usdhc2_dat3_pad = 176 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | 177 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL); 178 #endif 179 180 static void setup_iomux_uart(void) 181 { 182 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 183 } 184 185 #ifdef CONFIG_FSL_QSPI 186 static int board_qspi_init(void) 187 { 188 /* Set the clock */ 189 enable_qspi_clk(0); 190 191 return 0; 192 } 193 #endif 194 195 #ifdef CONFIG_FSL_ESDHC 196 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 197 {USDHC1_BASE_ADDR, 0, 4}, 198 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 199 {USDHC2_BASE_ADDR, 0, 8}, 200 #else 201 {USDHC2_BASE_ADDR, 0, 4}, 202 #endif 203 }; 204 205 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) 206 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) 207 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) 208 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) 209 210 int board_mmc_getcd(struct mmc *mmc) 211 { 212 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 213 int ret = 0; 214 215 switch (cfg->esdhc_base) { 216 case USDHC1_BASE_ADDR: 217 ret = !gpio_get_value(USDHC1_CD_GPIO); 218 break; 219 case USDHC2_BASE_ADDR: 220 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 221 ret = 1; 222 #else 223 imx_iomux_v3_setup_pad(usdhc2_cd_pad); 224 gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); 225 gpio_direction_input(USDHC2_CD_GPIO); 226 227 /* 228 * Since it is the DAT3 pin, this pin is pulled to 229 * low voltage if no card 230 */ 231 ret = gpio_get_value(USDHC2_CD_GPIO); 232 233 imx_iomux_v3_setup_pad(usdhc2_dat3_pad); 234 #endif 235 break; 236 } 237 238 return ret; 239 } 240 241 int board_mmc_init(bd_t *bis) 242 { 243 #ifdef CONFIG_SPL_BUILD 244 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 245 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, 246 ARRAY_SIZE(usdhc2_emmc_pads)); 247 #else 248 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 249 #endif 250 gpio_direction_output(USDHC2_PWR_GPIO, 0); 251 udelay(500); 252 gpio_direction_output(USDHC2_PWR_GPIO, 1); 253 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 254 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); 255 #else 256 int i, ret; 257 258 /* 259 * According to the board_mmc_init() the following map is done: 260 * (U-Boot device node) (Physical Port) 261 * mmc0 USDHC1 262 * mmc1 USDHC2 263 */ 264 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 265 switch (i) { 266 case 0: 267 imx_iomux_v3_setup_multiple_pads( 268 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 269 gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); 270 gpio_direction_input(USDHC1_CD_GPIO); 271 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 272 273 gpio_direction_output(USDHC1_PWR_GPIO, 0); 274 udelay(500); 275 gpio_direction_output(USDHC1_PWR_GPIO, 1); 276 break; 277 case 1: 278 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 279 imx_iomux_v3_setup_multiple_pads( 280 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); 281 #else 282 imx_iomux_v3_setup_multiple_pads( 283 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 284 #endif 285 gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); 286 gpio_direction_output(USDHC2_PWR_GPIO, 0); 287 udelay(500); 288 gpio_direction_output(USDHC2_PWR_GPIO, 1); 289 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 290 break; 291 default: 292 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); 293 return -EINVAL; 294 } 295 296 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 297 if (ret) { 298 printf("Warning: failed to initialize mmc dev %d\n", i); 299 return ret; 300 } 301 } 302 #endif 303 return 0; 304 } 305 #endif 306 307 #ifdef CONFIG_USB_EHCI_MX6 308 #ifndef CONFIG_DM_USB 309 310 #define USB_OTHERREGS_OFFSET 0x800 311 #define UCTRL_PWR_POL (1 << 9) 312 313 static iomux_v3_cfg_t const usb_otg_pads[] = { 314 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), 315 }; 316 317 /* At default the 3v3 enables the MIC2026 for VBUS power */ 318 static void setup_usb(void) 319 { 320 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 321 ARRAY_SIZE(usb_otg_pads)); 322 } 323 324 int board_usb_phy_mode(int port) 325 { 326 if (port == 1) 327 return USB_INIT_HOST; 328 else 329 return usb_phy_mode(port); 330 } 331 332 int board_ehci_hcd_init(int port) 333 { 334 u32 *usbnc_usb_ctrl; 335 336 if (port > 1) 337 return -EINVAL; 338 339 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 340 port * 4); 341 342 /* Set Power polarity */ 343 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 344 345 return 0; 346 } 347 #endif 348 #endif 349 350 #ifdef CONFIG_FEC_MXC 351 /* 352 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only 353 * be used for ENET1 or ENET2, cannot be used for both. 354 */ 355 static iomux_v3_cfg_t const fec1_pads[] = { 356 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 357 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 358 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 359 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 360 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 361 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 362 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 363 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 364 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 365 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 366 }; 367 368 static iomux_v3_cfg_t const fec2_pads[] = { 369 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 370 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 371 372 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 373 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 374 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 375 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 376 377 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 378 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 379 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 380 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 381 }; 382 383 static void setup_iomux_fec(int fec_id) 384 { 385 if (fec_id == 0) 386 imx_iomux_v3_setup_multiple_pads(fec1_pads, 387 ARRAY_SIZE(fec1_pads)); 388 else 389 imx_iomux_v3_setup_multiple_pads(fec2_pads, 390 ARRAY_SIZE(fec2_pads)); 391 } 392 393 int board_eth_init(bd_t *bis) 394 { 395 setup_iomux_fec(CONFIG_FEC_ENET_DEV); 396 397 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, 398 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 399 } 400 401 static int setup_fec(int fec_id) 402 { 403 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 404 int ret; 405 406 if (fec_id == 0) { 407 /* 408 * Use 50M anatop loopback REF_CLK1 for ENET1, 409 * clear gpr1[13], set gpr1[17]. 410 */ 411 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 412 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); 413 } else { 414 /* 415 * Use 50M anatop loopback REF_CLK2 for ENET2, 416 * clear gpr1[14], set gpr1[18]. 417 */ 418 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 419 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); 420 } 421 422 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); 423 if (ret) 424 return ret; 425 426 enable_enet_clk(1); 427 428 return 0; 429 } 430 431 int board_phy_config(struct phy_device *phydev) 432 { 433 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); 434 435 if (phydev->drv->config) 436 phydev->drv->config(phydev); 437 438 return 0; 439 } 440 #endif 441 442 #ifdef CONFIG_VIDEO_MXS 443 static iomux_v3_cfg_t const lcd_pads[] = { 444 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 445 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 446 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 447 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 448 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), 449 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), 450 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), 451 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), 452 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), 453 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), 454 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), 455 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), 456 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), 457 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), 458 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 459 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 460 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 461 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 462 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 463 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 464 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 465 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 466 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 467 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 468 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 469 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 470 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 471 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 472 473 /* LCD_RST */ 474 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 475 476 /* Use GPIO for Brightness adjustment, duty cycle = period. */ 477 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 478 }; 479 480 static int setup_lcd(void) 481 { 482 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); 483 484 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 485 486 /* Reset the LCD */ 487 gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); 488 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); 489 udelay(500); 490 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); 491 492 /* Set Brightness to high */ 493 gpio_request(IMX_GPIO_NR(1, 8), "backlight"); 494 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); 495 496 return 0; 497 } 498 #endif 499 500 int board_early_init_f(void) 501 { 502 setup_iomux_uart(); 503 504 return 0; 505 } 506 507 int board_init(void) 508 { 509 /* Address of boot parameters */ 510 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 511 512 #ifdef CONFIG_FEC_MXC 513 setup_fec(CONFIG_FEC_ENET_DEV); 514 #endif 515 516 #ifdef CONFIG_USB_EHCI_MX6 517 #ifndef CONFIG_DM_USB 518 setup_usb(); 519 #endif 520 #endif 521 522 #ifdef CONFIG_FSL_QSPI 523 board_qspi_init(); 524 #endif 525 526 #ifdef CONFIG_VIDEO_MXS 527 setup_lcd(); 528 #endif 529 530 return 0; 531 } 532 533 #ifdef CONFIG_CMD_BMODE 534 static const struct boot_mode board_boot_modes[] = { 535 /* 4 bit bus width */ 536 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, 537 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 538 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, 539 {NULL, 0}, 540 }; 541 #endif 542 543 int board_late_init(void) 544 { 545 #ifdef CONFIG_CMD_BMODE 546 add_board_boot_modes(board_boot_modes); 547 #endif 548 549 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 550 env_set("board_name", "EVK"); 551 552 if (is_mx6ul_9x9_evk()) 553 env_set("board_rev", "9X9"); 554 else 555 env_set("board_rev", "14X14"); 556 #endif 557 558 return 0; 559 } 560 561 int checkboard(void) 562 { 563 if (is_mx6ul_9x9_evk()) 564 puts("Board: MX6UL 9x9 EVK\n"); 565 else 566 puts("Board: MX6UL 14x14 EVK\n"); 567 568 return 0; 569 } 570 571 #ifdef CONFIG_SPL_BUILD 572 #include <linux/libfdt.h> 573 #include <spl.h> 574 #include <asm/arch/mx6-ddr.h> 575 576 577 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 578 .grp_addds = 0x00000030, 579 .grp_ddrmode_ctl = 0x00020000, 580 .grp_b0ds = 0x00000030, 581 .grp_ctlds = 0x00000030, 582 .grp_b1ds = 0x00000030, 583 .grp_ddrpke = 0x00000000, 584 .grp_ddrmode = 0x00020000, 585 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK 586 .grp_ddr_type = 0x00080000, 587 #else 588 .grp_ddr_type = 0x000c0000, 589 #endif 590 }; 591 592 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK 593 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 594 .dram_dqm0 = 0x00000030, 595 .dram_dqm1 = 0x00000030, 596 .dram_ras = 0x00000030, 597 .dram_cas = 0x00000030, 598 .dram_odt0 = 0x00000000, 599 .dram_odt1 = 0x00000000, 600 .dram_sdba2 = 0x00000000, 601 .dram_sdclk_0 = 0x00000030, 602 .dram_sdqs0 = 0x00003030, 603 .dram_sdqs1 = 0x00003030, 604 .dram_reset = 0x00000030, 605 }; 606 607 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 608 .p0_mpwldectrl0 = 0x00000000, 609 .p0_mpdgctrl0 = 0x20000000, 610 .p0_mprddlctl = 0x4040484f, 611 .p0_mpwrdlctl = 0x40405247, 612 .mpzqlp2ctl = 0x1b4700c7, 613 }; 614 615 static struct mx6_lpddr2_cfg mem_ddr = { 616 .mem_speed = 800, 617 .density = 2, 618 .width = 16, 619 .banks = 4, 620 .rowaddr = 14, 621 .coladdr = 10, 622 .trcd_lp = 1500, 623 .trppb_lp = 1500, 624 .trpab_lp = 2000, 625 .trasmin = 4250, 626 }; 627 628 struct mx6_ddr_sysinfo ddr_sysinfo = { 629 .dsize = 0, 630 .cs_density = 18, 631 .ncs = 1, 632 .cs1_mirror = 0, 633 .walat = 0, 634 .ralat = 5, 635 .mif3_mode = 3, 636 .bi_on = 1, 637 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ 638 .rtt_nom = 0, 639 .sde_to_rst = 0, /* LPDDR2 does not need this field */ 640 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ 641 .ddr_type = DDR_TYPE_LPDDR2, 642 .refsel = 0, /* Refresh cycles at 64KHz */ 643 .refr = 3, /* 4 refresh commands per refresh cycle */ 644 }; 645 646 #else 647 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 648 .dram_dqm0 = 0x00000030, 649 .dram_dqm1 = 0x00000030, 650 .dram_ras = 0x00000030, 651 .dram_cas = 0x00000030, 652 .dram_odt0 = 0x00000030, 653 .dram_odt1 = 0x00000030, 654 .dram_sdba2 = 0x00000000, 655 .dram_sdclk_0 = 0x00000030, 656 .dram_sdqs0 = 0x00000030, 657 .dram_sdqs1 = 0x00000030, 658 .dram_reset = 0x00000030, 659 }; 660 661 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 662 .p0_mpwldectrl0 = 0x00000000, 663 .p0_mpdgctrl0 = 0x41570155, 664 .p0_mprddlctl = 0x4040474A, 665 .p0_mpwrdlctl = 0x40405550, 666 }; 667 668 struct mx6_ddr_sysinfo ddr_sysinfo = { 669 .dsize = 0, 670 .cs_density = 20, 671 .ncs = 1, 672 .cs1_mirror = 0, 673 .rtt_wr = 2, 674 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 675 .walat = 0, /* Write additional latency */ 676 .ralat = 5, /* Read additional latency */ 677 .mif3_mode = 3, /* Command prediction working mode */ 678 .bi_on = 1, /* Bank interleaving enabled */ 679 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 680 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 681 .ddr_type = DDR_TYPE_DDR3, 682 .refsel = 0, /* Refresh cycles at 64KHz */ 683 .refr = 1, /* 2 refresh commands per refresh cycle */ 684 }; 685 686 static struct mx6_ddr3_cfg mem_ddr = { 687 .mem_speed = 800, 688 .density = 4, 689 .width = 16, 690 .banks = 8, 691 .rowaddr = 15, 692 .coladdr = 10, 693 .pagesz = 2, 694 .trcd = 1375, 695 .trcmin = 4875, 696 .trasmin = 3500, 697 }; 698 #endif 699 700 static void ccgr_init(void) 701 { 702 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 703 704 writel(0xFFFFFFFF, &ccm->CCGR0); 705 writel(0xFFFFFFFF, &ccm->CCGR1); 706 writel(0xFFFFFFFF, &ccm->CCGR2); 707 writel(0xFFFFFFFF, &ccm->CCGR3); 708 writel(0xFFFFFFFF, &ccm->CCGR4); 709 writel(0xFFFFFFFF, &ccm->CCGR5); 710 writel(0xFFFFFFFF, &ccm->CCGR6); 711 writel(0xFFFFFFFF, &ccm->CCGR7); 712 } 713 714 static void spl_dram_init(void) 715 { 716 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 717 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 718 } 719 720 void board_init_f(ulong dummy) 721 { 722 ccgr_init(); 723 724 /* setup AIPS and disable watchdog */ 725 arch_cpu_init(); 726 727 /* iomux and setup of i2c */ 728 board_early_init_f(); 729 730 /* setup GP timer */ 731 timer_init(); 732 733 /* UART clocks enabled and gd valid - init serial console */ 734 preloader_console_init(); 735 736 /* DDR initialization */ 737 spl_dram_init(); 738 739 /* Clear the BSS. */ 740 memset(__bss_start, 0, __bss_end - __bss_start); 741 742 /* load/boot image from boot device */ 743 board_init_r(NULL, 0); 744 } 745 #endif 746